This is a shortcoming of our current SimpleScalar-derived detailed CPU
model that functionally executes instructions as it fetches them; loads
and stores are applied to a flat global functional memory object at
thiat point. Thus the functional results (i.e. load values) reflect a
sequentially consistent ordering based on the order in which the
instructions are fetched. The timing reflects the Alpha relaxed
consistency model, which in reality could have provided different
functional results. This is actually not an uncommon situation in
multiprocessor simulators.
We're actively working on fixing this... our new detailed CPU model and
memory hierarchy merge functional and timing simulation, so the
functional and timing effects of whatever your memory consistency model
are will both be accurately reflected. We're close but not all the way
done with this. Stay tuned...
Steve
Sean Ryan Leventhal wrote:
I am reading the documentation found at
http://m5.eecs.umich.edu/docs/memory.html, which claims that you
identify the result of a memory operation before determining the
timing. How do you then maintain memory consistency in multiprocessor
systems?
Sean
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