Jos, The latency parameter in SimpleMemBank determines when the block is ready to return to the caches. The first chunk returned over the bus is assumed to be the critical chunk, with the arrival times of subsequent chunks calculated from the bus parameters (latency, width, etc).
Erik On Sun, 4 Dec 2005, Jos Delbar wrote: > Hi, > > SimpleScalar allows you to set two parameters for the memory access > latency: one for the first chunk and another for the following chunks. How > is this modelled in M5? Is the BaseMem latency parameter used for each > memory access, or is the cost of subsequent accesses also reduced in some > way? > > Thanks, > > - Jos Delbar > [EMAIL PROTECTED] > > > ------------------------------------------------------- > This SF.net email is sponsored by: Splunk Inc. Do you grep through log files > for problems? Stop! Download the new AJAX search engine that makes > searching your log files as easy as surfing the web. DOWNLOAD SPLUNK! > http://ads.osdn.com/?ad_id=7637&alloc_id=16865&op=click > _______________________________________________ > m5sim-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/m5sim-users > ------------------------------------------------------- This SF.net email is sponsored by: Splunk Inc. Do you grep through log files for problems? Stop! Download the new AJAX search engine that makes searching your log files as easy as surfing the web. DOWNLOAD SPLUNK! http://ads.osdn.com/?ad_id=7637&alloc_id=16865&op=click _______________________________________________ m5sim-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/m5sim-users
