If you're looking at bus statistics, the reason is that there is no bus
between the CPU and the L1; they're directly connected. You can look at
the number of accesses to the L1 and calculate the bandwidth yourself
(assuming some fixed size per access).
Steve
Anupama Kunchakara wrote:
Hi all
In the m5 stats file we are not able to get the traffic from CPU to L1..
We have the traffic from L1->L2,L2->L3 and from L3->memory..
Please tell me what would be the reason for this ?
Ur help will be highly appreciated..
Thank you
--
Anupama
Graduate Student
Computer Science Department
(Webmaster for Lamar Career Center)
Lamar University
Texas
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