At first glance your .py file below looks fine to me. Although there
are no physical addresses in syscall emulation mode, there is a
translation step where the address space ID (ASID) is pasted into the
upper bits of the address to make addresses unique across different
processes (see the dummyTranslation() method in cpu/exec_context.hh).
The problem you're having is that these ASIDs are currently only set for
different threads on the same CPU (i.e. using SMT on FullCPU). For
example, in the SimpleCPU constructor (cpu/simple/cpu.cc) the ASID
argument of the ExecContext constructor it calls is hard-wired to 0. If
you change that code to give each workload a different ASID you should
be fine.
In syscall emulation mode, we've only used the MP model to run parallel
apps, so this hasn't been a problem for us. (We've only used the SMT
model to run multiprogram workloads as well, so as we found recently the
code doesn't support running parallel apps on SMT either.) We're
currently embarking on a pretty thorough revamping of the memory system
that will provide a more realistic physical address space for syscall
emulation mode (among other things), so hopefully by the time M5 2.0
comes out this won't be a problem. That won't happen soon though (we're
shooting for this summer).
Steve
Mihara Tomonobu wrote:
dear M5 team,
I would like to simulate Multiprocessing on CMP,
but I wonder how to describe .py file.
I think that address space of workloads in NO_FullSim mode is not
translated to physical address, because workloads belonging other
process share data (as my m5stats.txt).
Can I separate virtual address, or transelate virtual address into physical
address easily?
Thanks.
----
Tomonobu Mihara, Japan
hear is my .py file:
from m5 import *
## Memory Configuration#################################
## L1Cache configuration ###########
class BaseL1Cache(BaseCache):
size = '64kB'
assoc = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
class IL1(BaseL1Cache):
latency = Parent.clock.period
mshrs = 8
class DL1(BaseL1Cache):
latency = 3 * Parent.clock.period
mshrs = 32
## L2Cache configuration ###########
class ToL2Bus(Bus):
width = 64
clock = Parent.clock.period
class L2(BaseCache):
size = '2MB'
assoc = '32ki'
block_size = 64
latency = 10 * Parent.clock.period
mshrs = 92
tgts_per_mshr = 16
class ToMemBus(Bus):
width = 16
clock = 1 * Parent.clock.period
class SDRAM(BaseMemory):
latency = 100 * Parent.clock.period
uncacheable_latency = 1000 * Parent.clock.period
## CPU Configuration #################################################
class CPU(SimpleCPU):
icache = IL1(out_bus=Parent.toL2bus)
dcache = DL1(out_bus=Parent.toL2bus)
## Benchmark configuration #####
class Bzip_test_random(LiveProcess):
executable = '/home/mihara/m5_1.1//bench/bin/bzip200.peak.ev6'
cmd = 'bzip200.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random 2'
class Gzip_test_random(LiveProcess):
executable = '/home/mihara/m5_1.1/bench/bin/gzip00.peak.ev6'
cmd = 'gzip00.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random'
## system configuration ########
class Simple_CMP(Root):
Coherence = CoherenceProtocol(protocol='msi')
cpu0 = CPU()
cpu1 = CPU()
SimpleCPU.max_insts_any_thread = 1000000000
Workload = Bzip_test_random()
Workload2 = Gzip_test_random()
cpu0.workload = Workload
cpu1.workload = Workload2
cpu0.dcache.protocol = Coherence
cpu1.dcache.protocol = Coherence
cpu0.icache.protocol = Coherence
cpu1.icache.protocol = Coherence
l2 = L2(in_bus=Parent.toL2bus, out_bus=Parent.toMembus)
toMembus = ToMemBus()
sdram = SDRAM(in_bus=Parent.toMembus)
toL2bus = ToL2Bus()
hier = HierParams(do_data=False, do_events=True)
root = Simple_CMP()
hear is my m5stats.txt:
cpu0.dcache.protocol.hwpf_invalid 0 #
hard prefetch misses to invalid blocks
cpu0.dcache.protocol.read_invalid 3280420 #
read misses to invalid blocks
cpu0.dcache.protocol.snoop_inv_exclusive 0 #
Invalidate snoops on exclusive blocks
cpu0.dcache.protocol.snoop_inv_invalid 0 #
Invalidate snoops on invalid blocks
cpu0.dcache.protocol.snoop_inv_modified 0 #
Invalidate snoops on modified blocks
cpu0.dcache.protocol.snoop_inv_owned 0 #
Invalidate snoops on owned blocks
cpu0.dcache.protocol.snoop_inv_shared 0 #
Invalidate snoops on shared blocks
cpu0.dcache.protocol.snoop_read_exclusive 0 #
read snoops on exclusive blocks
cpu0.dcache.protocol.snoop_read_modified 9178 #
read snoops on modified blocks
cpu0.dcache.protocol.snoop_read_owned 0 #
read snoops on owned blocks
cpu0.dcache.protocol.snoop_read_shared 698 #
read snoops on shared blocks
cpu0.dcache.protocol.snoop_readex_exclusive 0
# readEx snoops on exclusive blocks
cpu0.dcache.protocol.snoop_readex_modified 8087 #
readEx snoops on modified blocks
cpu0.dcache.protocol.snoop_readex_owned 0 #
readEx snoops on owned blocks
cpu0.dcache.protocol.snoop_readex_shared 939 #
readEx snoops on shared blocks
cpu0.dcache.protocol.snoop_upgrade_owned 0 #
upgrade snoops on owned blocks
cpu0.dcache.protocol.snoop_upgrade_shared 20654 #
upgradee snoops on shared blocks
cpu0.dcache.protocol.snoop_writeinv_exclusive 0
# WriteInvalidate snoops on exclusive blocks
cpu0.dcache.protocol.snoop_writeinv_invalid 0
# WriteInvalidate snoops on invalid blocks
cpu0.dcache.protocol.snoop_writeinv_modified 0
# WriteInvalidate snoops on modified blocks
cpu0.dcache.protocol.snoop_writeinv_owned 0 #
WriteInvalidate snoops on owned blocks
cpu0.dcache.protocol.snoop_writeinv_shared 0 #
WriteInvalidate snoops on shared blocks
cpu0.dcache.protocol.swpf_invalid 0 #
soft prefetch misses to invalid blocks
cpu0.dcache.protocol.write_invalid 1570494 #
write misses to invalid blocks
cpu0.dcache.protocol.write_owned 0 #
write misses to owned blocks
cpu0.dcache.protocol.write_shared 1264388 #
write misses to shared blocks
cpu0.dcache.read_accesses 197405037 #
number of read accesses(hits+misses)
cpu0.dcache.read_avg_miss_latency 32.049379 #
average read miss latency
cpu0.dcache.read_avg_mshr_miss_latency 29.049379 #
average read mshr miss latency
cpu0.dcache.read_hits 194124658 #
number of read hits
cpu0.dcache.read_miss_latency 105134110 #
number of read miss cycles
cpu0.dcache.read_miss_rate 0.016618 #
miss rate for read accesses
cpu0.dcache.read_misses 3280379 #
number of read misses
cpu0.dcache.read_mshr_miss_latency 95292973 #
number of read MSHR miss cycles
cpu0.dcache.read_mshr_miss_rate 0.016618 #
mshr miss rate for read accesses
cpu0.dcache.read_mshr_misses 3280379 #
number of read MSHR misses
cpu0.dcache.replacements 4820203 #
number of replacements
cpu0.dcache.sampled_refs 4821192 #
Sample count of references to valid blocks.
cpu0.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
cpu0.dcache.tagsinuse 1021.875637 #
Cycle average of tags in use
cpu0.dcache.total_refs 318591490 #
Total number of references to valid blocks.
cpu0.dcache.warmup_cycle 1074702 #
Cycle when the warmup percentage was hit.
cpu0.dcache.write_accesses 126277977 #
number of write accesses(hits+misses)
cpu0.dcache.write_avg_miss_latency 49.706157 #
average write miss latency
cpu0.dcache.write_avg_mshr_miss_latency 46.706157 #
average write mshr miss latency
cpu0.dcache.write_hits 123443095 #
number of write hits
cpu0.dcache.write_miss_latency 140911090 #
number of write miss cycles
cpu0.dcache.write_miss_rate 0.022450 #
miss rate for write accesses
cpu0.dcache.write_misses 2834882 #
number of write misses
cpu0.dcache.write_mshr_miss_latency 132406444 #
number of write MSHR miss cycles
cpu0.dcache.write_mshr_miss_rate 0.022450 #
mshr miss rate for write accesses
cpu0.dcache.write_mshr_misses 2834882 #
number of write MSHR misses
cpu0.dcache.writebacks 2817301 #
number of writebacks
cpu0.dcache_stall_cycles 246045200 #
DCache total stall cycles
cpu1.dcache.protocol.hwpf_invalid 0 #
hard prefetch misses to invalid blocks
cpu1.dcache.protocol.read_invalid 7802184 #
read misses to invalid blocks
cpu1.dcache.protocol.snoop_inv_exclusive 0 #
Invalidate snoops on exclusive blocks
cpu1.dcache.protocol.snoop_inv_invalid 0 #
Invalidate snoops on invalid blocks
cpu1.dcache.protocol.snoop_inv_modified 0 #
Invalidate snoops on modified blocks
cpu1.dcache.protocol.snoop_inv_owned 0 #
Invalidate snoops on owned blocks
cpu1.dcache.protocol.snoop_inv_shared 0 #
Invalidate snoops on shared blocks
cpu1.dcache.protocol.snoop_read_exclusive 0 #
read snoops on exclusive blocks
cpu1.dcache.protocol.snoop_read_modified 24797 #
read snoops on modified blocks
cpu1.dcache.protocol.snoop_read_owned 0 #
read snoops on owned blocks
cpu1.dcache.protocol.snoop_read_shared 632 #
read snoops on shared blocks
cpu1.dcache.protocol.snoop_readex_exclusive 0
# readEx snoops on exclusive blocks
cpu1.dcache.protocol.snoop_readex_modified 4479 #
readEx snoops on modified blocks
cpu1.dcache.protocol.snoop_readex_owned 0 #
readEx snoops on owned blocks
cpu1.dcache.protocol.snoop_readex_shared 123 #
readEx snoops on shared blocks
cpu1.dcache.protocol.snoop_upgrade_owned 0 #
upgrade snoops on owned blocks
cpu1.dcache.protocol.snoop_upgrade_shared 11360 #
upgradee snoops on shared blocks
cpu1.dcache.protocol.snoop_writeinv_exclusive 0
# WriteInvalidate snoops on exclusive blocks
cpu1.dcache.protocol.snoop_writeinv_invalid 0
# WriteInvalidate snoops on invalid blocks
cpu1.dcache.protocol.snoop_writeinv_modified 0
# WriteInvalidate snoops on modified blocks
cpu1.dcache.protocol.snoop_writeinv_owned 0 #
WriteInvalidate snoops on owned blocks
cpu1.dcache.protocol.snoop_writeinv_shared 0 #
WriteInvalidate snoops on shared blocks
cpu1.dcache.protocol.swpf_invalid 0 #
soft prefetch misses to invalid blocks
cpu1.dcache.protocol.write_invalid 1484238 #
write misses to invalid blocks
cpu1.dcache.protocol.write_owned 0 #
write misses to owned blocks
cpu1.dcache.protocol.write_shared 2759207 #
write misses to shared blocks
cpu1.dcache.read_accesses 148432033 #
number of read accesses(hits+misses)
cpu1.dcache.read_avg_miss_latency 35.165257 #
average read miss latency
cpu1.dcache.read_avg_mshr_miss_latency 32.165257 #
average read mshr miss latency
cpu1.dcache.read_hits 140629849 #
number of read hits
cpu1.dcache.read_miss_latency 274365802 #
number of read miss cycles
cpu1.dcache.read_miss_rate 0.052564 #
miss rate for read accesses
cpu1.dcache.read_misses 7802184 #
number of read misses
cpu1.dcache.read_mshr_miss_latency 250959250 #
number of read MSHR miss cycles
cpu1.dcache.read_mshr_miss_rate 0.052564 #
mshr miss rate for read accesses
cpu1.dcache.read_mshr_misses 7802184 #
number of read MSHR misses
cpu1.dcache.replacements 9269317 #
number of replacements
cpu1.dcache.sampled_refs 9270337 #
Sample count of references to valid blocks.
cpu1.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
cpu1.dcache.tagsinuse 1004.269822 #
Cycle average of tags in use
cpu1.dcache.total_refs 198379247 #
Total number of references to valid blocks.
cpu1.dcache.warmup_cycle 27342581 #
Cycle when the warmup percentage was hit.
cpu1.dcache.write_accesses 59233179 #
number of write accesses(hits+misses)
cpu1.dcache.write_avg_miss_latency 44.297244 #
average write miss latency
cpu1.dcache.write_avg_mshr_miss_latency 41.297244 #
average write mshr miss latency
cpu1.dcache.write_hits 54989856 #
number of write hits
cpu1.dcache.write_miss_latency 187967516 #
number of write miss cycles
cpu1.dcache.write_miss_rate 0.071638 #
miss rate for write accesses
cpu1.dcache.write_misses 4243323 #
number of write misses
cpu1.dcache.write_mshr_miss_latency 175237547 #
number of write MSHR miss cycles
cpu1.dcache.write_mshr_miss_rate 0.071638 #
mshr miss rate for write accesses
cpu1.dcache.write_mshr_misses 4243323 #
number of write MSHR misses
cpu1.dcache.writebacks 4213385 #
number of writebacks
cpu1.dcache_stall_cycles 462333318 #
DCache total stall cycles
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