I'm trying to generate a config file capable of fast forwarding a chunk
of simulation using a functional model before switching to the more
detailed timing model. For starters, I'm trying to get two SimpleCPUs to
work. I'm instantiating them as follows:
root=Root()
root.cpu0 = SimpleCPU()
root.cpu1 = SimpleCPU()
bm = Benchmarks.Helloworld()
root.cpu0.workload = bm
root.cpu1.workload = bm
root.sampler = Sampler(phase0_cpus = [root.cpu0], phase1_cpus =
[root.cpu1], periods = [4e3, 1e15])
root.toMembus = Bus(width=64, clock=1*Parent.clock.period)
root.ram = SDRAM(in_bus=Parent.toMembus)
The Helloworld benchmark is a simple "Helloworld" app which takes 8106
cycles on a single SimpleCPU. Reading the code in sampler.cc, I take it
that the two parameters are meant to be how long to execute each phase
for, so in the above example phase_0 will run for 4e3 (4000) cycles and
phase_1 will run for 1e15 cycles. Again from reading the code, after
phase_1 m5 would like to return to phase_0 but for some reason can't so
will exit the simulation. When I run m5 with this config file and
turning on tracing of the Sampler I get:
[EMAIL PROTECTED]:ALPHA_SE$ ./m5.debug -d ../../tmp/
../../configs/myconfig/Run.py --Root.trace.flags="Sampler"
M5 Simulator System
Copyright (c) 2001-2005
The Regents of The University of Michigan
All Rights Reserved
This code is part of the M5 simulator, developed by Nathan Binkert,
Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,
and Andrew Schultz.
M5 compiled on Jan 19 2006 15:31:21
M5 executing on bovat.cl.cam.ac.uk
M5 simulation started Thu Jan 19 15:37:51 2006
command line: ./m5.debug -d ../../tmp/ ../../configs/myconfig/Run.py
--Root.trace.flags=Sampler
warn: Entering event queue. Starting simulation...
0: Event_ad1a90: New switch event curTick=0 when=4000
4000: sampler: switching CPUs 4000: sampler: Done switching CPUs
4000: Event_ad1ae0: New switch event curTick=4000
when=1000000000004000
Hello world on stdout!
Hello world on stderr!
Terminating simulation -- syscall caused exit
Simulation complete at Thu Jan 19 15:37:55 2006
Which looks reasonable (apart from the Event_ad etc. garbage?). However,
looking at the statistics I see:
cpu0.idle_fraction 0.493462 # Percentage of idle
cycles
cpu0.not_idle_fraction 0.506538 # Percentage of non-idle
cycles
cpu0.numCycles 0 # number of cpu cycles
simulated
cpu0.num_insts 0 # Number of instructions
executed
cpu0.num_refs 0 # Number of memory
references
cpu0.workload.MainMem.page_count 3 # total number of pages
allocated
cpu0.workload.MainMem.page_mem 24 # total size of memory
pages allocated
cpu0.workload.MainMem.ptab_accesses 6051 # total page table
accessess
cpu0.workload.MainMem.ptab_miss_rate 0.0008 # first level page table
miss rate
cpu0.workload.MainMem.ptab_misses 5 # total first level page
table misses
cpu0.workload.PROG:num_syscalls 6 # Number of system calls
cpu1.idle_fraction 0.493462 # Percentage of idle
cycles
cpu1.not_idle_fraction 0.506538 # Percentage of non-idle
cycles
cpu1.numCycles 4106 # number of cpu cycles
simulated
cpu1.num_insts 4106 # Number of instructions
executed
cpu1.num_refs 1424 # Number of memory
references
So some of the statistics for cpu0 are zero (indicating that cpu0 hasn't run)
but not all and the number of instructions executed by cpu1 is what I
would expect if cpu0 had actually run for 4000 cycles (8106-4000=4106). Any
ideas as to the discrepancy?
Thanks,
James
--
[EMAIL PROTECTED]
http://www.cl.cam.ac.uk/~jrs53/
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