If you are trying to simulate a perfect unified cache, the easiest way
to do it would be to take the main memory object and put it where the
cache is and give it the latency of the cache.
If you want to do something more complex, like simulate a perfect
instruction cache but a realistic data cache, then you probably would
need to hack up a new cache model that simply always acted as if it had
a hit. Another approach is to just make the cache extremely large and
highly associative; you would still pay for compulsory misses, but
that's it.
Steve
Krit Athikulwongse wrote:
Dear M5 team,
I am trying to simulate a system with ideal caches. I used to use
sim-alpha, and it has this option for L2 cache. I would like to know
whether M5 has this option or not. If so, could you please direct me to
the class/object that I should look at?
If not, a method that comes up in my mind right now, besides using very
big cache (few MB) with 0-cycle hit latency, is to hack one of the
class/object in the memory hierarchy to return latency of 0 no matter
the accesses hit or miss.
Thank you,
Krit
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