Filip Hellebaut wrote:
Hi Steve,
In the tutorial presented on ISCA05 they mention on slide 34 some
capabilities of sampling. You can for example fastforward a number of
instructions while warming up the cashes.
When I try to do this I get some problems. If the parameter "do_events"
is set to true it seems to work. Although, when I take a closer look I
see that the number of executed instructions is not correct anymore. In
the example below it should fastforward 1000 instructions. In reality it
are only 17 instructions because the SimpleCPU spends a lot of ticks
waiting for incoming data from the memory hierarchy.
The Sampler period parameters are in ticks, not in instructions, so
you're right, you're only getting 17 instructions executed in 1000
cycles because the caches are cold and you're mostly waiting on misses.
I thought this
problem would be solved by setting the "do_events" parameter to false.
Conceptually, yes... this would make the cache misses instantaneous and
thus give you 1 CPI.
This results in a segmentation error.
Is there something wrong in my config file? What exactly is going wrong?
I believe the problem is that you must have do_events on when you do the
detailed simulation (it doesn't make sense to model the CPU in
excruciating detail but not the memory), and there's no way to have the
Sampler change do_events for you.
That said, we should give an error message rather than segfaulting...
could you send a backtrace of where the segfault happens?
How did you warmup caches while fastforwarding?
We do it the way you had it set up initially, with do_events=True. If
you run for more than 1K cycles the caches start to fill up and you
start to approach 1 CPI. Since no events get scheduled while the CPU is
waiting for memory, the simulation runtime is actually more proportional
to the number of instructions than the number of ticks anyway, so the
performance penalty of do_events=True at this point isn't as bad as it
might seem.
What we usually do in practice (for full-system simulations, which is
almost all we do ourselves) is use a fast run with no caches and
do_events=False to boot the machine and drop checkpoints, then start
from the checkpoints with a warmup period followed by detailed simulation.
For non-full-system runs we use SimpleScalar EIO traces generates by
SimpleScalar's sim-eio. (M5 can read EIO traces but doesn't generate them.)
root = Root()
root.hier = HierParams(do_data=False, do_events=True)
root.toL2Bus = ToL2Bus()
root.l2 = L2(in_bus=Parent.toL2Bus, out_bus=Parent.toMemBus)
root.dl1 = DL1(out_bus=Parent.toL2Bus)
root.il1 = IL1(out_bus=Parent.toL2Bus)
root.toMemBus = ToMemBus()
root.ram = SDRAM(in_bus=Parent.toMemBus)
root.cpu = [ SimpleCPU(icache = Parent.il1, dcache = Parent.dl1, width =
1), DetailedCPU(icache = Parent.il1, dcache = Parent.dl1)]
last = Benchmarks.Swim()
root.cpu[0].workload = last
root.cpu[1].workload = last
phase0_cpus = [ root.cpu[0] ]
phase1_cpus = [ root.cpu[1] ]
root.sampler = [ Sampler(periods = [1e3, 2e3], phase0_cpus=phase0_cpus,
phase1_cpus = phase1_cpus ) ]
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