[m5sim-users] connecting L1 to L2

[justin kemp]

Hi!!!

To M5 team and sim users.

I am new to m5 and trying to learn m5.

I have studied the following code and i would like to understand how L1 cache is connected to L2 cache.

 

For example the particular lines

 

ToL2Bus

ToMemBus

 

I want to understand that in detail what is the purpose of those two lines.

 

 

from m5 import *

## Memory Configuration#################################
## L1Cache configuration ###########

class BaseL1Cache(BaseCache):
    size = '64kB'
    assoc = 2
    block_size = 64
    mshrs = 4
    tgts_per_mshr = 8

class IL1(BaseL1Cache):
    latency = Parent.clock.period
    mshrs = 8
class DL1(BaseL1Cache):
    latency = 3 * Parent.clock.period
    mshrs = 32

## L2Cache configuration ###########

class ToL2Bus(Bus):
    width = 64
    clock = Parent.clock.period

class L2(BaseCache):
    size = '2MB'
    assoc = '32ki'
    block_size = 64
    latency = 10 * Parent.clock.period
    mshrs = 92
    tgts_per_mshr = 16

class ToMemBus(Bus):
    width = 16
    clock = 1 * Parent.clock.period

class SDRAM(BaseMemory):
    latency = 100 * Parent.clock.period
    uncacheable_latency = 1000 * Parent.clock.period
## CPU Configuration #################################################

class CPU(SimpleCPU):
    icache = IL1(out_bus=Parent.toL2bus)
    dcache = DL1(out_bus= Parent.toL2bus)

## Benchmark configuration #####

class Bzip_test_random(LiveProcess):
    executable = '/home/mihara/m5_1.1//bench/bin/bzip200.peak.ev6'
    cmd = 'bzip200.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random 2'

class Gzip_test_random(LiveProcess):
    executable = '/home/mihara/m5_1.1/bench/bin/gzip00.peak.ev6'
    cmd = 'gzip00.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random'


## system configuration ########

class Simple_CMP(Root):
    Coherence = CoherenceProtocol(protocol='msi')
    cpu0 = CPU()
    cpu1 = CPU()
    SimpleCPU.max_insts_any_thread = 1000000000
    Workload = Bzip_test_random()
    Workload2 = Gzip_test_random()   
    cpu0.workload = Workload
    cpu1.workload = Workload2   
    cpu0.dcache.protocol = Coherence
    cpu1.dcache.protocol = Coherence
    cpu0.icache.protocol = Coherence
    cpu1.icache.protocol = Coherence
    l2 = L2(in_bus=Parent.toL2bus, out_bus=Parent.toMembus)
    toMembus = ToMemBus()
    sdram = SDRAM(in_bus=Parent.toMembus)
    toL2bus = ToL2Bus()
    hier = HierParams(do_data=False, do_events=True)

root = Simple_CMP()