[m5sim-users] Re: m5sim-users digest, Vol 1 #235 - 1 msg

Arpan Solanki Mon, 17 Apr 2006 16:51:02 -0700

Does m5 have classes for switch or router for network on chip. If they are where can i find them. Also where are the classes for network on chip.

On 4/13/06, [EMAIL PROTECTED] < [EMAIL PROTECTED]> wrote:

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Today's Topics:

   1. connecting L1 to L2 (justin kemp)

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Message: 1
Date: Thu, 13 Apr 2006 14:55:56 -0500
From: "justin kemp" < [EMAIL PROTECTED]>
To: [email protected]
Subject: [m5sim-users] connecting L1 to L2

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Hi!!!
To M5 team and sim users.
I am new to m5 and trying to learn m5.
I have studied the following code and i would like to understand how L1
cache is connected to L2 cache.

For example the particular lines

ToL2Bus
ToMemBus

I want to understand that in detail what is the purpose of those two lines.

from m5 import *

## Memory Configuration#################################
## L1Cache configuration ###########

class BaseL1Cache(BaseCache):
    size =3D '64kB'
    assoc =3D 2
    block_size =3D 64
    mshrs =3D 4
    tgts_per_mshr =3D 8

class IL1(BaseL1Cache):
    latency =3D Parent.clock.period
    mshrs =3D 8
class DL1(BaseL1Cache):
    latency =3D 3 * Parent.clock.period
    mshrs =3D 32

## L2Cache configuration ###########

class ToL2Bus(Bus):
    width =3D 64
    clock =3D Parent.clock.period

class L2(BaseCache):
    size =3D '2MB'
    assoc =3D '32ki'
    block_size =3D 64
    latency =3D 10 * Parent.clock.period
    mshrs =3D 92
    tgts_per_mshr =3D 16

class ToMemBus(Bus):
    width =3D 16
    clock =3D 1 * Parent.clock.period

class SDRAM(BaseMemory):
    latency =3D 100 * Parent.clock.period
    uncacheable_latency =3D 1000 * Parent.clock.period
## CPU Configuration #################################################

class CPU(SimpleCPU):
    icache =3D IL1(out_bus=3DParent.toL2bus)
    dcache =3D DL1(out_bus=3DParent.toL2bus)

## Benchmark configuration #####

class Bzip_test_random(LiveProcess):
    executable =3D '/home/mihara/m5_1.1//bench/bin/bzip200.peak.ev6'
    cmd =3D 'bzip200.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random 2=
'

class Gzip_test_random(LiveProcess):
    executable =3D '/home/mihara/m5_1.1/bench/bin/gzip00.peak.ev6'
    cmd =3D 'gzip00.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random'

## system configuration ########

class Simple_CMP(Root):
    Coherence =3D CoherenceProtocol(protocol=3D'msi')
    cpu0 =3D CPU()
    cpu1 =3D CPU()
    SimpleCPU.max_insts_any_thread =3D 1000000000
    Workload =3D Bzip_test_random()
    Workload2 =3D Gzip_test_random()
    cpu0.workload =3D Workload
    cpu1.workload =3D Workload2
    cpu0.dcache.protocol =3D Coherence
    cpu1.dcache.protocol =3D Coherence
    cpu0.icache.protocol =3D Coherence
    cpu1.icache.protocol =3D Coherence
    l2 =3D L2(in_bus=3DParent.toL2bus, out_bus=3DParent.toMembus)
    toMembus =3D ToMemBus()
    sdram =3D SDRAM(in_bus=3DParent.toMembus)
    toL2bus =3D ToL2Bus()
    hier =3D HierParams(do_data=3DFalse, do_events=3DTrue)

root =3D Simple_CMP()

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<div>Hi!!!</div>
<div>To M5 team and sim users.</div>
<div>I am new to m5 and trying to learn m5.</div>
<div>I have studied the following code and i would like to understand how L=
1 cache is connected to L2 cache.</div>
<div> </div>
<div>For example the particular lines</div>
<div> </div>
<div>ToL2Bus</div>
<div>ToMemBus</div>
<div> </div>
<div>I want to understand that in detail what is the purpose of those two l=
ines.</div>
<div> </div>
<div> </div>
<div>from m5 import *<br><br>## Memory Configuration#######################=
##########<br>## L1Cache configuration ###########<br><br>class BaseL1Cache=
(BaseCache):<br>    size =3D '64kB'<br>    as=
soc =3D 2<br>    block_size =3D 64
<br>    mshrs =3D 4<br>    tgts_per_mshr =3D =
8<br><br>class IL1(BaseL1Cache):<br>    latency =3D Parent.c=
lock.period<br>    mshrs =3D 8<br>class DL1(BaseL1Cache):<br=
>    latency =3D 3 * Parent.clock.period<br>  &nbs=
p; mshrs =3D 32<br><br>
## L2Cache configuration ###########<br><br>class ToL2Bus(Bus):<br> &n=
bsp;  width =3D 64<br>    clock =3D Parent.clock.period=
<br><br>class L2(BaseCache):<br>    size =3D '2MB'<br> =
   assoc =3D '32ki'<br>    block_size =3D 64<br>&n=
bsp;   latency =3D 10 *=20
Parent.clock.period<br>    mshrs =3D 92<br>  &nbsp=
; tgts_per_mshr =3D 16<br><br>class ToMemBus(Bus):<br>    wi=
dth =3D 16<br>    clock =3D 1 * Parent.clock.period<br><br>c=
lass SDRAM(BaseMemory):<br>    latency =3D 100 * Parent.cloc=
k.period
<br>    uncacheable_latency =3D 1000 * Parent.clock.period<b=
r>## CPU Configuration #################################################<br=
><br>class CPU(SimpleCPU):<br>    icache =3D IL1(out_bus=3DP=
arent.toL2bus)<br>    dcache =3D DL1(out_bus=3D
Parent.toL2bus)<br><br>## Benchmark configuration #####<br><br>class Bzip_t=
est_random(LiveProcess):<br>    executable =3D '/home/mihara=
/m5_1.1//bench/bin/bzip200.peak.ev6'<br>    cmd =3D 'bzip200=
.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random 2'
<br><br>class Gzip_test_random(LiveProcess):<br>    executab=
le =3D '/home/mihara/m5_1.1/bench/bin/gzip00.peak.ev6'<br>  &nbsp=
; cmd =3D 'gzip00.peak.ev6 /home/mihara/m5_1.1/bench/input/test.random'<br>=
<br><br>## system configuration ########
<br><br>class Simple_CMP(Root):<br>    Coherence =3D Coheren=
ceProtocol(protocol=3D'msi')<br>    cpu0 =3D CPU()<br> =
   cpu1 =3D CPU()<br>    SimpleCPU.max_insts_any_t=
hread =3D 1000000000<br>    Workload =3D Bzip_test_random()<=
br>    Workload2 =3D Gzip_test_random()   =20
<br>    cpu0.workload =3D Workload<br>    cpu=
1.workload =3D Workload2    <br>    cpu0.dcac=
he.protocol =3D Coherence<br>    cpu1.dcache.protocol =3D Co=
herence<br>    cpu0.icache.protocol =3D Coherence<br> &=
nbsp;  cpu1.icache.protocol =3D Coherence
<br>    l2 =3D L2(in_bus=3DParent.toL2bus, out_bus=3DParent.=
toMembus)<br>    toMembus =3D ToMemBus()<br>  &nbs=
p; sdram =3D SDRAM(in_bus=3DParent.toMembus)<br>    toL2bus =
=3D ToL2Bus()<br>    hier =3D HierParams(do_data=3DFalse, do=
_events=3DTrue)<br>
<br>root =3D Simple_CMP()<br> </div>

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[m5sim-users] Re: m5sim-users digest, Vol 1 #235 - 1 msg

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