I believe Steve is exactly correct, the out-of-order model is not
enforcing a dependency between your two instructions. The way to fix
it is to force a dependancy to a register (for example the result of
the load). You need to do this both in the decoder and in the code
that executes the instruction.
For example for the rpcc instruction (this code may be a little bit
newer than yours, but same idea):
/* Rb is a fake dependency so here is a fun way to get the parser
to understand that. */
Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
and in some code:
inline uint32_t cycleCounter(uint32_t dep)
{
uint32_t res;
asm volatile ("rpcc %0, %1" : "=r"(res) : "r" (dep) : "memory");
return res;
}
t1 = cycleCounter(trash);
for (x = 0; x < count; x++) {
trash = readl(addr);
t2 = cycleCounter(trash);
}
Ali
On Apr 26, 2006, at 9:59 PM, Steve Reinhardt wrote:
My guess would be that it has to do with the out-of-order
scheduling in the detailed CPU. If the instruction that reads
curTick has no dependence on the read or write instructions, then
it will get executed out-of-order while the read or write is still
stalled.
I remember that we ran into this problem ourselves but I don't
remember the details of how we solved it... Ali or Nate, can you
help here?
Steve
Richard R. Zhang wrote:
Hi Lisa and all M5 users,
I find something strange with the io access latency. Could you
give me a hint with it?
I have added a new instruction to the alpha isa. This instruction
can get the curTick in M5. It seems to work correctly. So, I plan
to use it to measure the time in the guest OS. Then, I added some
statements to the ns83820 driver. These statements compute the
time used by the driver irq routine and the io access(just compute
the of writel and readl). But the results below puzzled me, and I
can't explain it. These results come from a netperf maerts test
under Sampler mode, and the memory configuration is STE.
---------------------------------------------------------------------
--------
| | CacheCPU mode |
DetailedCPU mode |
---------------------------------------------------------------------
--------
|avg.io read time | 1581 cycles |
40 cycles |
---------------------------------------------------------------------
--------
|avg.io write time | 1561 cycles |
9 cycles |
---------------------------------------------------------------------
--------
I don't know why the io access time in CacheCPU is much bigger
than it in DetailedCPU. I think that the time in CacheCPU mode
should less than which in DetailedCPU mode, at least equal to it.
This is strange to me. Could anybody give me the explain with it?
Thanks a lot.
Best wishes,
Richard R. Zhang
2006-04-26
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