This error comes as a result of two interfaces believeing that they
are responsible for an address. Typically this happens when you assign
the same address range to two devices or have address ranges that overlap.
It is also possible that a cache and a device connected as slaves on the
bus and both think they are responsible for the address. In this case you
would need to explicitly list the cache's address range as being
everything but the devices address range.
If your network device is connected between two levels of caches this is
what I susspect is going on. Look at the config/fullsys/Memory.py file
where we define the MemoryOCS system, you should see a line that says:
self.l2.addr_range = [ AddrRange(0x0, 0x80008ffffff),
AddrRange(0x8000a000000, 0x803ffffffff) ]
This is removing the address range of the NIC that is connected between
the L1 and L2 from the L2's response address range.
-Ron
On Thu, 27 Apr 2006, Arpan Solanki wrote:
Hi!!!
I am trying to simulate network on chip.
Can any one tell me what this error suggests.
I guess this means there are two busses ending on one simobject. This is
what it suggests. But in my configuration file it is not the case.
If any one wants me to be more specific plz do ask.
Fatal: Two suppliers for address 0x102380 on bus fromSwitch0_bus
@ cycle 24
[sendAddr:m5/mem/bus/bus.cc, line 383]
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