My simulation terminates by giving me the line
"warn: Entering event queue. Starting simulation...
Terminating simulation -- halt instruction encountered"
I checked the archives and have seen some similar problems but What can I do to fix this?
Bushra
Following is my run.py
###################################################################3
from m5 import *
AddToPath('../M5/m5_1.1/m5/python/m5/')
AddToPath('../M5/m5_1.1/m5-test')
AddToPath('../M5/m5_1.1/m5/python/m5/objects')
import Benchmarks
from MemConfig import *
from FuncUnitConfig import *
## Memory Configuration#################################
## L1Cache configuration ###########
class BaseL1Cache(BaseCache):
size = '32kB'
assoc = 1
block_size = 32
mshrs = 4
tgts_per_mshr = 8
class IL1(BaseL1Cache):
latency = Parent.clock.period
mshrs = 8
class DL1(BaseL1Cache):
latency = 1 * Parent.clock.period
mshrs = 32
## L2Cache configuration ###########
class ToL2Bus(Bus):
width = 64
clock = Parent.clock.period
class L2(BaseCache):
size = '4MB'
assoc = '8'
block_size = 64
latency = 14 * Parent.clock.period
mshrs = 92
tgts_per_mshr = 16
class ToMemBus(Bus):
width = 16
clock = 1 * Parent.clock.period
class SDRAM(BaseMemory):
latency = 100 * Parent.clock.period
uncacheable_latency = 1 * Parent.clock.period
## CPUConfiguration#################################################
class CPU(SimpleCPU):
icache = IL1(out_bus=Parent.toL2bus)
dcache = DL1(out_bus=Parent.toL2bus)
## system configuration ########
class Simple_CMP(Root):
Coherence = CoherenceProtocol(protocol='msi')
cpu0 = CPU()
cpu1 = CPU()
cpu2 = CPU()
cpu3 = CPU()
cpu0.workload = Benchmarks.mesa()
cpu0.max_insts_any_thread = 100
cpu1.workload = Benchmarks.art()
cpu1.max_insts_any_thread = 100
cpu0.dcache.protocol = Coherence
cpu1.dcache.protocol = Coherence
cpu0.icache.protocol = Coherence
cpu1.icache.protocol = Coherence
cpu2.workload = Benchmarks.mesa()
cpu2.max_insts_any_thread = 100
cpu3.workload = Benchmarks.art()
cpu3.max_insts_any_thread = 100
cpu2.dcache.protocol = Coherence
cpu3.dcache.protocol = Coherence
cpu2.icache.protocol = Coherence
cpu3.icache.protocol = Coherence
l2 = L2(in_bus=Parent.toL2bus, out_bus=Parent.toMembus)
toMembus = ToMemBus()
sdram = SDRAM(in_bus=Parent.toMembus)
toL2bus = ToL2Bus()
hier = HierParams(do_data=False, do_events=True)
root = Simple_CMP()
###################################################################
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