Hi,
I am using m5 v2.0b1 (patched) and I get some errors in FS mode when
adding a cache hierarchy to the cpu using the addTwoLevelCacheHierarchy
function.
The errors vary for each different cpu model I use, and they raise soon
after the simulation starts.
So, for:
* AtomicSimpleCPU:
I get:
m5.opt: build/ALPHA_FS/mem/request.hh:229: int Request::getThreadNum():
Assertion `validCpuAndThreadNums' failed.
* TimingSimpleCPU:
here m5.opt segfaults, so I ran instead m5.debug with gdb to see what's
going on. I got the following:
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 46912511183616 (LWP 5234)]
0x00000000004dce76 in std::list<MSHR*, std::allocator<MSHR*> >::erase
(this=0x19e29f8, __position={_M_node = 0x21}) at list.tcc:97
97 iterator __ret = __position._M_node->_M_next;
* DetailedO3CPU:
I get the following error:
m5.opt: build/ALPHA_FS/mem/cache/tags/cache_tags_impl.hh:329: typename
CacheTags<Tags, Compression>::BlkType* CacheTags<Tags,
Compression>::handleFill(typename Tags::BlkType*, MSHR*, unsigned int,
PacketList&) [with Tags = LRU, Compression = NullCompression]: Assertion
`target->getOffset(blkSize) + target->getSize() <= blkSize' failed.
Program aborted at cycle 2
Aborted
The script I am using is the following (it is a cut-down version of the
original fs.py --except for the lines that define the hierarchy-- and
simulates a single system):
------------------------------------ my_fs.py
-----------------------------------
import optparse, os, sys
import m5
from m5.objects import *
m5.AddToPath('../common')
from FSConfig import *
from SysPaths import *
from Benchmarks import *
parser = optparse.OptionParser()
parser.add_option("-m", "--maxtick", type="int")
parser.add_option("-b", "--benchmark", action="store", type="string",
dest="benchmark",
help="Specify the benchmark to run. Available benchmarks: %s"\
% DefinedBenchmarks)
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
cpu = TimingSimpleCPU()
mem_mode = 'timing'
cpu.clock = '2GHz'
ic = BaseCache(size='32kB', assoc=1, latency=1, block_size=32, mshrs=4,
tgts_per_mshr=8)
dc = BaseCache(size='32kB', assoc=4, latency=1, block_size=32, mshrs=4,
tgts_per_mshr=8)
l2c = BaseCache(size='2MB', assoc=2, latency=1, block_size=64, mshrs=10,
tgts_per_mshr=5)
cpu.addTwoLevelCacheHierarchy(ic,dc, l2c)
if options.benchmark:
if options.benchmark not in Benchmarks:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
bm = Benchmarks[options.benchmark]
else:
bm = [Machine()]
root = Root(clock = '1GHz', system = makeLinuxAlphaSystem(mem_mode, bm[0]))
root.system.cpu = cpu
cpu.connectMemPorts(root.system.membus)
cpu.mem = root.system.physmem
m5.instantiate(root)
if options.maxtick:
maxtick = options.maxtick
else:
maxtick = -1
exit_event = m5.simulate(maxtick)
while exit_event.getCause() == "checkpoint":
m5.checkpoint(root, "cpt.%d")
exit_event = m5.simulate(maxtick - m5.curTick())
print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause()
---------------------------------------------------------------------------------
Thanks in advance,
Nick.
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