Hi everyone,
I have been investigating the issue about the L1 data cache. It seems
like the problem occurs as soon as a writeback from the L1 cache occurs
- I have pasted the trace and config at the end of this message.
Maybe someone can help me figuring out where the problem is. Thanks in
advance!
Regards,
Jonas
Here is the trace:
./build/ALPHA_SE/m5.opt --trace-flags="Cache Bus" ./configs/jonas/se1.py
-c tests/test-progs/hello/bin/alpha/linux/hello 2>&1 | tail
2769: system.membus: found addr 0x7b40 on device 0
2769: system.toL2Bus: recvAtomic: packet src 2 dest -1 addr 0x74970
cmd ReadReq
2769: system.toL2Bus: found addr 0x74970 on device 0
2769: system.membus: recvAtomic: packet src 1 dest -1 addr 0x74940
cmd ReadReq
2769: system.membus: found addr 0x74940 on device 0
2769: system.cpu.dcache: replacement: replacing 7c970 with 74970:
writeback
2769: system.toL2Bus: recvAtomic: packet src 2 dest -1 addr 0x7c970
cmd WriteReqNoAck
2769: system.toL2Bus: found addr 0x7c970 on device 0
m5.opt: build/ALPHA_SE/mem/request.hh:229: int Request::getThreadNum():
Assertion `validCpuAndThreadNums' failed.
Program aborted at cycle 2769
This is the config script I used:
# Simple test script
#
# "m5 test.py"
import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('../common')
from FullO3Config import *
parser = optparse.OptionParser()
parser.add_option("-c", "--cmd",
default="../../tests/test-progs/hello/bin/alpha/linux/hello",
help="The binary to run in syscall emulation mode.")
parser.add_option("-o", "--options", default="",
help="The options to pass to the binary, use \" \"
around the entire\
string.")
parser.add_option("-i", "--input", default="",
help="A file of input to give to the binary.")
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
process = LiveProcess()
process.executable = options.cmd
process.cmd = options.cmd + " " + options.options
if options.input != "":
process.input = options.input
if options.timing:
cpu = TimingSimpleCPU()
elif options.detailed:
cpu = DetailedO3CPU()
else:
cpu = AtomicSimpleCPU()
cpu.workload = process
# ----------------------
# Base L1 Cache
# ----------------------
class L1(BaseCache):
latency = 1
block_size = 8 #32
mshrs = 1
tgts_per_mshr = 1
# ----------------------
# Base L2 Cache
# ----------------------
class L2(BaseCache):
block_size = 64
latency = 100
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
system.toL2Bus = Bus()
system.l2c = L2(size='1MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.port
# connect l2c to membus
system.l2c.mem_side = system.membus.port
cpu.addPrivateSplitL1Caches(L1(size = '16kB', assoc = 1),
L1(size = '16kB', assoc = 1))
cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
root = Root(system = system)
if options.timing or options.detailed:
root.system.mem_mode = 'timing'
# instantiate configuration
m5.instantiate(root)
# simulate until program terminates
if options.maxtick:
exit_event = m5.simulate(options.maxtick)
else:
exit_event = m5.simulate()
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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