Hi,m5-users，
I have checked FuncUnitConfig.py and find the RdWrPort is configurated with
"count = 4". Does that mean that the CPU can execute 4 Load/Restore insts
simultaneously?
If my L1 caches are not configurated with multi-ports, so my cache cannot
be accessed by more than one insts simultaneously. In this case , the
configuration about RdWrPort above will be invalid, is that right?
Btw: Can my L1 cache be configurated with multi-ports? If so, how to
maintain the conherence of Regs file because of multi-accesses to L1 cache
simultaneously? I want to know whether that case is considered or not in M5.
Thanks and Best Regards!
xiaojun.chen
[EMAIL PROTECTED]
2007-01-05
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