Hi all, I have a L2 cache problem in the M5 1.1 SE mode. When I run 2 different programs on 2 different cpus, I find that these 2 programs access the same address. For example, program A accesses it's data and read the address 0x01e5f2. Later, program B accesses it's data and read the same address 0x01e5f2, too.
I dumped the req->paddr in the cache module, and It seems that the memory references of program A and program B are overlapped. This will make the L2 miss of program B become a L2 hit. Maybe I misunderstand the m5 cache model. If I am not, is there any easy way to separate the memory references of multi-programs in L2 cache? Then the measurement will be more accurate in the M5 SE mode. Thanks, Meng-Ju _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
