After the IEW stage executes an instruction, if it detects a memory order violation or if the memory system is blocked it sends a squash signal which eventually reaches the fetch stage and results in a pipeline flush and possible a cache access.
I don't know what does it mean when m5 determines the memory system is blocked, but as far as memory order violations go, I think it would be more efficient and realistic to just reissue the instructions needed instead of flushing the whole pipeline and forcing the fetch stage to decode the instructions again (and possibly trigger a cache access, since it is quite possible that the fetch stage is in another cache line by then). Is there any reason why M5 chooses to flush the whole pipeline instead of replaying/reissuing the offending instructions (loads). Thanks, Alex
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