How about getting rid of the L2 entirely and giving main memory the
latency of an L2 hit? If I understand you correctly that would give you
what you're looking for.
Prabhat Kumar wrote:
Hi All,
I want to simulate a system in which I have only L1 cache latency,i.e.,
if I have a miss in the L1 cache and the data is fetched from L2 cache or
from memory still I want to observe just the L1 cache latency. Can I make
the latency of L2 cache/memory to be 0 to achieve this? Or is there any
parameter in M5 configuration, like max load latency or something, which I
can set so as to fulfill my objective.
Thanks,
Prabhat
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