On May 18, 2007, at 4:17 PM, Sujay Phadke wrote:
Hello,
I want to try and model a multicore architecture in M5. As
example system would be:
4 cores (lets say alpha)
private L1 caches, shared L2
DRAM model (RDRAM or SRAM, with power modes control)
I want to build this configuration, and run benchmark tests on
this, and tweak the power mode transitioning for the DRAM modules,
to see what policy works best in achieving low power.
So, what I want to know is:
1) Can I model such a system?
Yes
2) Do DRAM models already exist for M5?
Yes, see src/mem/dram.cc although there has been absolutely no
validation that the dram model has been is valid after it was
integrated with m5 (e.g. we may have messed something up integrating it)
3) Will it be possible to migrate pages from one DRAM rank to another?
I have no idea, you should look at the code.
4) Can I get traces if the pages accessed most frequently by tests
like splash, or spec2000?
You would have to add some code to the dram model to output the page
accesses in a format that would be good for this.
Ali
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