Hi Geoff, I don't see that problem in the head of our tree... why don't you just update from there.
Steve On 7/16/07, Steve Reinhardt <[EMAIL PROTECTED]> wrote:
Hi Geoff, I don't see that problem in the head of our tree... why don't you just update from there. Steve On 7/16/07, Geoffrey Blake <[EMAIL PROTECTED]> wrote: > I've found a bug in the beta 3 release of M5. When running with more > than one CPU and no L2 cache, I get an invalid transition abort from the > coherence code while booting linux in FS mode. > > Just running this command line will produce the error: > > > > build/ALPHA_FS/m5.opt fs.py –t –n 4 –caches > > > > I have looked at the problem in GDB and it appears the problem is > stemming from a packet getting on the memory bus that has a command > MemCmd::WriteReq, which is causing the error. > > > > Geoff > > _______________________________________________ > m5-users mailing list > m5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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