Hi, I implement different page allocation algorithms(virtual to physical address translation algorithm) based on current DRAM model in full system(m5_2.0b). After running simulations(benchmark is ValStream), I could see more than 20% difference in average DRAM access latency within all these algorithms, but almost 0% difference in sim_ticks. Is that because the caculated dram latency is not used? Can anybody explain that to me? Thanks.
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