import m5
from m5.objects import *

#
# This is a sample of detailed SDRAM configuration file
#

#TimingITB
class TIMINGITB(TimingITB):
    size = 48
    vpsize = '4kB'

#TimingDTB    
class TIMINGDTB(TimingDTB):
    size = 64
    vpsize = '4kB'

# Virtual to physical address translation
# different page placement policy

# sequential page placement
class SEQUENTIAL(SequentialAddrTranslate):
    ptab_size = '16kB'
    page_size = '4kB'    

# random page placement
class RANDOM(RandomAddrTranslate):
    ptab_size = '16kB'
    page_size = '4kB'
    
# bank hopping random page placement
class BANKHOPRD(BankhoprdAddrTranslate):
    ptab_size = '16kB'
    page_size = '4kB'
    
# bank hopping sequential page placement
class BANKHOPSQ(BankhopsqAddrTranslate):
    ptab_size = '16kB'
    page_size = '4kB'
       
class LUB(LUBAddrTranslate):
    ptab_size = '16kB'
    page_size = '4kB'
    
class HYBRID_AF8(Hybrid_AF8):
    ptab_size = '16kB'
    page_size = '4kB'
    
class HYBRID_AF8_LRA8(Hybrid_AF8_LRA8):
    ptab_size = '16kB'
    page_size = '4kB'
    
class HYBRID(HybridAddrTranslate):
    ptab_size = '16kB'
    page_size = '4kB'
    

class DetailedSdram(DRAMMemory):
    timing_itb = TIMINGITB()    # timing instruction TLB
    timing_dtb = TIMINGDTB()    # timing data TLB
    addr_convert = SEQUENTIAL()