Hi Tracy,
It appears as though you're using M5 v2.0b1. There was a bug in 2.0b1
where if the out-of-order cpu speculatively issued a load to an
address that wasn't part of main memory a panic would occur.
Upgrading to 2.0b3 will probably fix your problem.
Ali
On Aug 22, 2007, at 4:51 PM, [EMAIL PROTECTED] wrote:
Hi,
I am using O3CPU model to run simulations. The benchmark I use is
ValStream. I run 100million or more instructions, and meet this
problem:
warn: This DRAM module has not been tested with the new memory
system at all!
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1
00:00:00 2006
Listening for console connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port
7000
warn: Entering event queue @ 0. Starting simulation...
warn: cycle 245000: Quiesce instruction encountered, halting fetch!
warn: cycle 266000: Quiesce instruction encountered, halting fetch!
warn: cycle 318500: fault (itbmiss) detected @ PC 0x000000
panic: Unable to find destination for addr: 80867e50
@ cycle 20572 971000
[findPort:build/ALPHA_FS/mem/bus.cc, line 154]
If I use TimingSimpleCPU/AtomicSimpleCPU, the simulation can finish
correctly. Is anyone know what the problem is?
Thanks,
Tracy
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