Hi,
I am running m5_2.0b3 by using O3CPU model and ValStream* benchmark.
//////////////////////////////////////////
The error message I got is like:
warn: This DRAM module has not been tested with the new memory system at all!
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: Entering event queue @ 0. Starting simulation...
panic: Invalid transition
@ cycle 1786604790002
[invalidTransition:build/ALPHA_FS/mem/cache/coherence/coherence_protocol.cc,
line 465]
Program aborted at cycle 1786604790002
//////////////////////////////////////////
Here is my configuration file:
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
print "test memory mode is %s" %test_mem_mode
DriveCPUClass.clock = '2GHz'
if options.benchmark:
try:
bm = Benchmarks[options.benchmark]
except KeyError:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
else:
if options.dual:
bm = [SysConfig(), SysConfig()]
else:
bm = [SysConfig()]
if m5.build_env['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
elif m5.build_env['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
else:
m5.panic("incapable of building non-alpha or non-sparc full system!")
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
np = options.num_cpus
if options.l2cache:
test_sys.l2 = L2Cache(size = '2MB')
test_sys.tol2bus = Bus()
test_sys.l2.cpu_side = test_sys.tol2bus.port
test_sys.l2.mem_side = test_sys.membus.port
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
for i in xrange(np):
if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
if options.l2cache:
test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
else:
test_sys.cpu[i].connectMemPorts(test_sys.membus)
test_sys.cpu[i].max_insts_all_threads = 1000000000
if len(bm) == 2:
if m5.build_env['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif m5.build_env['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(system=test_sys)
root.system.physmem = DetailedSdram(range = AddrRange(bm[0].mem()))
root.system.physmem.port = root.system.membus.port
for i in xrange(np):
test_sys.cpu[i].mem = root.system.physmem
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
Simulation.run(options, root, test_sys, FutureClass)
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command line is :
/home/tracy/m5_2.0b3/m5/build/ALPHA_FS/m5.opt -d
/home/tracy/m5_2.0b3/simulation/result/
--stats-file=/home/tracy/m5_2.0b3/simulation/result/ValStreamScale.sta
/home/tracy/m5_2.0b3/simulation/configs/none/fs.py -b ValStreamScale -d
--caches
Does anyone know what is the problem?
Thanks,
Rongrong
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