Ali, Thank you very much for your detailed reply.
The implementation of my algorithm must execute every cycle. In simplescalar, there is a sim-main function with a loop in it to emulate the pipeline every cycle. Is there the same function in M5? I think I should put my algorithm in that function to execute every cycle just like a stage of pipeline. In the mail list 2006, Steve said "MainMemory is used for running applications(like you are doing, via the Process object), while PhysicalMemory is used in full-system mode (when you're booting an operating system)......Unless you start using full-system mode, you will notuse PhysicalMemory or the MemoryController object (which serves as a switch to direct memory accesses either to a PhysicalMemory module or a memory-mapped device, depending on the physical address)." Does that mean the SE mode cannot be configured with a physical memory? And if we want to emulate a SDRAM, I must use the FS mode? Thanks a lot On 9/20/07, Ali Saidi <[EMAIL PROTECTED]> wrote: > > > > > On Sep 19, 2007, at 12:09 PM, laymanyang wrote: > > Hi all, > > I am new to M5 and I have some questions. If they look stupid, please > forgive me. > > > I want to add an out-of-order scheduling algorithm to physical memory access. > I need to deal with the packet to the physical memory every cycle. Where > should I add the algorithm to? > > Where ever you want. Derriving from the PhysicalMemory class probably > makes sense. > > Does the PhysicalMemory::MemoryPort::recvTiming(Packet *pkt) Function > execute every cycle or just when the packet comes? > > Just went a packet is received. > > Can I just add the scheduling here? > > You could, but it would be better to add it somewhere else in the physical > memory object. You don't need to be called every cycle, just the cycles > where you have work to do. So you should schedule an event that calls you > function in n cycles. This is done frequently by the caches and the devices > that support DMA. Take a look at dev/nsgige* and mem/caches/* for examples > on how to schedule events in the future. > > And which kind of simulation model should I choose, Full System or > Systemcall Emulation? > > Which ever one you need to do the experiments you want to do. > > > > I notice that the latency from memory->calculateLatency(pkt )is sent to > EventQueue by SimpleTimingPort::SendEvent(this, pkt, time).What is the > function of the EventQueue? > > It is a list of all the event the simulator needs to process. The > simulator processes the next event in the event queue until there are no > more events or the simulator exits. You can schedule events so that you get > a call back when a certain amount of time has elapsed (for example to send a > response in 100ns). > > Since only the latency is transferred to the eventqueue but the pkt is not. > How do they work collaboratively? What is the relationship between the CPU > and the EventQueue? > > See above. > > > Ali > > _______________________________________________ > m5-users mailing list > m5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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