Thanks, 

What do you mean "the caches and busses use a generic "port" model for 
interconnection " ? 

I think it means that I can design my bus-model that comply with the
generic "port" model so that the cache can exchange meseage or data 
with my bus-model. Right ? 

And, in m5, about the split-transaction bus (which you can combine with caches 
and bus bridges to make fairly complex hierarchies).

If I want to implement my bus-model , do I need to redesign a new bus bridge ?

Is it an interface between bus and cache ? 

And, your cacghe and bus models are event-driven or synchronous with a clock ?

thanks

Nov.  7  2007



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Today's Topics:

   1. Re: how to use m5 to do Network-on-chip simulation
      (Igor Andjelkovic)
   2. Re: how to use m5 to do Network-on-chip simulation
      (Steve Reinhardt)
   3. Re: how to use m5 to do Network-on-chip simulation ([EMAIL PROTECTED])
   4. Re: how to use m5 to do Network-on-chip simulation
      (Steve Reinhardt)
   5. Re: how to use m5 to do Network-on-chip simulation ([EMAIL PROTECTED])
   6. Re: Float in stats (Nathan Binkert)


----------------------------------------------------------------------

Message: 1
Date: Tue, 6 Nov 2007 14:40:21 -0800 (PST)
From: Igor Andjelkovic 
Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
To: M5 users mailing list 
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset="iso-8859-1"

Hi,

I am also a student who is interested in this topic.
Can anyone answer, please.

Igor

Tony Frank 
 wrote: Hi , 

I am a graduate student who is doing research work on Network-on-chip for 
multi-core computer. 

I need a simulator that can do simulation for network-on-chip with different
 topology, routing algorithm, router architecture, or different bus topology.

I also need to implement some blocks or units to the network-on-chip so that I
 can verify that my optimization design on the network-on-chip can improve
 performnce , power consumption and reliability, scalability. 

I also expect the simulator can generate the detailed information about 
 cycle-accurate, packet-level bus behavior.   

I found  "m5" simulator here. 

I do not know weather it can give me what I need.  

Would you please help me with it ? 

Or could you please recommmand other simulator for Network-on-chip?

thanks a lot !!!

Tony

Oct.  25  2007    __________________________________________________
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------------------------------

Message: 2
Date: Tue, 6 Nov 2007 15:58:04 -0800
From: "Steve Reinhardt" 
Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
To: "M5 users mailing list" 
Message-ID:
 <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=ISO-8859-1

M5 does not provide any general network models out of the box; our
only interconnect model at this point is a split-transaction bus
(which you can combine with caches and bus bridges to make fairly
complex hierarchies).

If you are interested in writing your own network models M5 would
provide a good substrate though.  We've recently updated our memory
system so that the caches and busses use a generic "port" model for
interconnection, so at the lowest level it would be easy to rip out a
bus and replace it with a network model of your choosing.

Our current cache coherence protocol relies on bus broadcast, so if
you want to do cache coherence across the network that would be
additional work.

Steve

On 11/6/07, Igor Andjelkovic  wrote:
> Hi,
>
> I am also a student who is interested in this topic.
> Can anyone answer, please.
>
> Igor
>
>
> Tony Frank 
 wrote:
>  Hi ,
>
> I am a graduate student who is doing research work on Network-on-chip for
> multi-core computer.
>
> I need a simulator that can do simulation for network-on-chip with different
>  topology, routing algorithm, router architecture, or different bus
> topology.
>
> I also need to implement some blocks or units to the network-on-chip so that
> I
>  can verify that my optimization design on the network-on-chip can improve
>  performnce , power consumption and reliability, scalability.
>
> I also expect the simulator can generate the detailed information about
>  cycle-accurate, packet-level bus behavior.
>
> I found  "m5" simulator here.
>
> I do not know weather it can give me what I need.
>
> Would you please help me with it ?
>
> Or could you please recommmand other simulator for Network-on-chip?
>
> thanks a lot !!!
>
> Tony
>
> Oct.  25  2007
>  __________________________________________________
> Do You Yahoo!?
> Tired of spam? Yahoo! Mail has the best spam protection around
> http://mail.yahoo.com
> _______________________________________________
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> m5-users@m5sim.org
> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>
>
>
>  __________________________________________________
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> Tired of spam? Yahoo! Mail has the best spam protection around
> http://mail.yahoo.com
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>


------------------------------

Message: 3
Date: Tue,  6 Nov 2007 20:33:27 -0500 (EST)
From: 
Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
To: M5 users mailing list 
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=us-ascii

Does M5 provide the message passing communication over
the network? Can I have several machines(each has its cpu and
memory) work together with data transfers among them?

Xin

---- Original message ----
>Date: Tue, 6 Nov 2007 15:58:04 -0800
>From: "Steve Reinhardt"   
>Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation  
>To: "M5 users mailing list" 
>
>M5 does not provide any general network models out of the box; our
>only interconnect model at this point is a split-transaction bus
>(which you can combine with caches and bus bridges to make fairly
>complex hierarchies).
>
>If you are interested in writing your own network models M5 would
>provide a good substrate though.  We've recently updated our memory
>system so that the caches and busses use a generic "port" model for
>interconnection, so at the lowest level it would be easy to rip out a
>bus and replace it with a network model of your choosing.
>
>Our current cache coherence protocol relies on bus broadcast, so if
>you want to do cache coherence across the network that would be
>additional work.
>
>Steve
>
>On 11/6/07, Igor Andjelkovic  wrote:
>> Hi,
>>
>> I am also a student who is interested in this topic.
>> Can anyone answer, please.
>>
>> Igor
>>
>>
>> Tony Frank 
 wrote:
>>  Hi ,
>>
>> I am a graduate student who is doing research work on Network-on-chip for
>> multi-core computer.
>>
>> I need a simulator that can do simulation for network-on-chip with different
>>  topology, routing algorithm, router architecture, or different bus
>> topology.
>>
>> I also need to implement some blocks or units to the network-on-chip so that
>> I
>>  can verify that my optimization design on the network-on-chip can improve
>>  performnce , power consumption and reliability, scalability.
>>
>> I also expect the simulator can generate the detailed information about
>>  cycle-accurate, packet-level bus behavior.
>>
>> I found  "m5" simulator here.
>>
>> I do not know weather it can give me what I need.
>>
>> Would you please help me with it ?
>>
>> Or could you please recommmand other simulator for Network-on-chip?
>>
>> thanks a lot !!!
>>
>> Tony
>>
>> Oct.  25  2007
>>  __________________________________________________
>> Do You Yahoo!?
>> Tired of spam? Yahoo! Mail has the best spam protection around
>> http://mail.yahoo.com
>> _______________________________________________
>> m5-users mailing list
>> m5-users@m5sim.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>
>>
>>
>>  __________________________________________________
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>> Tired of spam? Yahoo! Mail has the best spam protection around
>> http://mail.yahoo.com
>> _______________________________________________
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>> m5-users@m5sim.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>
>_______________________________________________
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>m5-users@m5sim.org
>http://m5sim.org/cgi-bin/mailman/listinfo/m5-users


------------------------------

Message: 4
Date: Tue, 6 Nov 2007 19:08:11 -0800
From: "Steve Reinhardt" 
Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
To: "M5 users mailing list" 
Message-ID:
 <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=ISO-8859-1

M5 models ethernet connections between machines, so if you want to
model a cluster-type system you're in good shape (though we just have
point-to-point links, so you'd need to write an ethernet switch model,
but that shouldn't be too hard).

My previous email was referring to on-chip networks, where you're
presumably connecting CPUs and caches within a single system.

Steve

On 11/6/07, [EMAIL PROTECTED]  wrote:
> Does M5 provide the message passing communication over
> the network? Can I have several machines(each has its cpu and
> memory) work together with data transfers among them?
>
> Xin
>
> ---- Original message ----
> >Date: Tue, 6 Nov 2007 15:58:04 -0800
> >From: "Steve Reinhardt" 
> >Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
> >To: "M5 users mailing list" 
> >
> >M5 does not provide any general network models out of the box; our
> >only interconnect model at this point is a split-transaction bus
> >(which you can combine with caches and bus bridges to make fairly
> >complex hierarchies).
> >
> >If you are interested in writing your own network models M5 would
> >provide a good substrate though.  We've recently updated our memory
> >system so that the caches and busses use a generic "port" model for
> >interconnection, so at the lowest level it would be easy to rip out a
> >bus and replace it with a network model of your choosing.
> >
> >Our current cache coherence protocol relies on bus broadcast, so if
> >you want to do cache coherence across the network that would be
> >additional work.
> >
> >Steve
> >
> >On 11/6/07, Igor Andjelkovic  wrote:
> >> Hi,
> >>
> >> I am also a student who is interested in this topic.
> >> Can anyone answer, please.
> >>
> >> Igor
> >>
> >>
> >> Tony Frank 
 wrote:
> >>  Hi ,
> >>
> >> I am a graduate student who is doing research work on Network-on-chip for
> >> multi-core computer.
> >>
> >> I need a simulator that can do simulation for network-on-chip with 
> >> different
> >>  topology, routing algorithm, router architecture, or different bus
> >> topology.
> >>
> >> I also need to implement some blocks or units to the network-on-chip so 
> >> that
> >> I
> >>  can verify that my optimization design on the network-on-chip can improve
> >>  performnce , power consumption and reliability, scalability.
> >>
> >> I also expect the simulator can generate the detailed information about
> >>  cycle-accurate, packet-level bus behavior.
> >>
> >> I found  "m5" simulator here.
> >>
> >> I do not know weather it can give me what I need.
> >>
> >> Would you please help me with it ?
> >>
> >> Or could you please recommmand other simulator for Network-on-chip?
> >>
> >> thanks a lot !!!
> >>
> >> Tony
> >>
> >> Oct.  25  2007
> >>  __________________________________________________
> >> Do You Yahoo!?
> >> Tired of spam? Yahoo! Mail has the best spam protection around
> >> http://mail.yahoo.com
> >> _______________________________________________
> >> m5-users mailing list
> >> m5-users@m5sim.org
> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
> >>
> >>
> >>
> >>  __________________________________________________
> >> Do You Yahoo!?
> >> Tired of spam? Yahoo! Mail has the best spam protection around
> >> http://mail.yahoo.com
> >> _______________________________________________
> >> m5-users mailing list
> >> m5-users@m5sim.org
> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
> >>
> >_______________________________________________
> >m5-users mailing list
> >m5-users@m5sim.org
> >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
> _______________________________________________
> m5-users mailing list
> m5-users@m5sim.org
> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>


------------------------------

Message: 5
Date: Tue,  6 Nov 2007 23:53:01 -0500 (EST)
From: 
Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
To: M5 users mailing list 
Message-ID: <[EMAIL PROTECTED]>
Content-Type: text/plain; charset=us-ascii

Sounds very good. What do you mean by "we just have"?
I am using M5 2.0b3. Is that ok?

Xin

---- Original message ----
>Date: Tue, 6 Nov 2007 19:08:11 -0800
>From: "Steve Reinhardt"   
>Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation  
>To: "M5 users mailing list" 
>
>M5 models ethernet connections between machines, so if you want to
>model a cluster-type system you're in good shape (though we just have
>point-to-point links, so you'd need to write an ethernet switch model,
>but that shouldn't be too hard).
>
>My previous email was referring to on-chip networks, where you're
>presumably connecting CPUs and caches within a single system.
>
>Steve
>
>On 11/6/07, [EMAIL PROTECTED]  wrote:
>> Does M5 provide the message passing communication over
>> the network? Can I have several machines(each has its cpu and
>> memory) work together with data transfers among them?
>>
>> Xin
>>
>> ---- Original message ----
>> >Date: Tue, 6 Nov 2007 15:58:04 -0800
>> >From: "Steve Reinhardt" 
>> >Subject: Re: [m5-users] how to use m5 to do Network-on-chip simulation
>> >To: "M5 users mailing list" 
>> >
>> >M5 does not provide any general network models out of the box; our
>> >only interconnect model at this point is a split-transaction bus
>> >(which you can combine with caches and bus bridges to make fairly
>> >complex hierarchies).
>> >
>> >If you are interested in writing your own network models M5 would
>> >provide a good substrate though.  We've recently updated our memory
>> >system so that the caches and busses use a generic "port" model for
>> >interconnection, so at the lowest level it would be easy to rip out a
>> >bus and replace it with a network model of your choosing.
>> >
>> >Our current cache coherence protocol relies on bus broadcast, so if
>> >you want to do cache coherence across the network that would be
>> >additional work.
>> >
>> >Steve
>> >
>> >On 11/6/07, Igor Andjelkovic  wrote:
>> >> Hi,
>> >>
>> >> I am also a student who is interested in this topic.
>> >> Can anyone answer, please.
>> >>
>> >> Igor
>> >>
>> >>
>> >> Tony Frank 
 wrote:
>> >>  Hi ,
>> >>
>> >> I am a graduate student who is doing research work on Network-on-chip for
>> >> multi-core computer.
>> >>
>> >> I need a simulator that can do simulation for network-on-chip with 
>> >> different
>> >>  topology, routing algorithm, router architecture, or different bus
>> >> topology.
>> >>
>> >> I also need to implement some blocks or units to the network-on-chip so 
>> >> that
>> >> I
>> >>  can verify that my optimization design on the network-on-chip can improve
>> >>  performnce , power consumption and reliability, scalability.
>> >>
>> >> I also expect the simulator can generate the detailed information about
>> >>  cycle-accurate, packet-level bus behavior.
>> >>
>> >> I found  "m5" simulator here.
>> >>
>> >> I do not know weather it can give me what I need.
>> >>
>> >> Would you please help me with it ?
>> >>
>> >> Or could you please recommmand other simulator for Network-on-chip?
>> >>
>> >> thanks a lot !!!
>> >>
>> >> Tony
>> >>
>> >> Oct.  25  2007
>> >>  __________________________________________________
>> >> Do You Yahoo!?
>> >> Tired of spam? Yahoo! Mail has the best spam protection around
>> >> http://mail.yahoo.com
>> >> _______________________________________________
>> >> m5-users mailing list
>> >> m5-users@m5sim.org
>> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>> >>
>> >>
>> >>
>> >>  __________________________________________________
>> >> Do You Yahoo!?
>> >> Tired of spam? Yahoo! Mail has the best spam protection around
>> >> http://mail.yahoo.com
>> >> _______________________________________________
>> >> m5-users mailing list
>> >> m5-users@m5sim.org
>> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>> >>
>> >_______________________________________________
>> >m5-users mailing list
>> >m5-users@m5sim.org
>> >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>> _______________________________________________
>> m5-users mailing list
>> m5-users@m5sim.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>
>_______________________________________________
>m5-users mailing list
>m5-users@m5sim.org
>http://m5sim.org/cgi-bin/mailman/listinfo/m5-users


------------------------------

Message: 6
Date: Wed, 7 Nov 2007 00:19:06 -0500 (EST)
From: Nathan Binkert 
Subject: Re: [m5-users] Float in stats
To: M5 users mailing list 
Message-ID: 

Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed

> I used the exitcallback to register a function which is called at the end of 
> simumations. I use floating point quantities in the simulations and wanted to 
> print them out in my own format in a file. This function opens a file, dumps 
> the required values into it at the end of simulation.
>
> This is working perfectly in SE mode. But in the FS mode, there is no file 
> being generated. The simulation ends (say when i do a ctrl-C) and dumps out 
> the standard stats,but somehow does not call this exit function.
This is certainly odd.  There should be no difference in FS and SE mode 
for this stuff.

Python has an atexit handler (in src/python/m5/simulate.py) which calls 
internal.core.doExitCleanup upon exiting python.  That python call 
actually is a wrapper for the c++ function doExitCleanup in 
src/sim/core.cc.

I'd suggest putting a breakpoint on doExitCleanup and make sure it's 
actually being called.  You should also verify that the callback is indeed 
making it onto the callback queue.

If that doesn't get you where you need to go, I can try and see if I can 
reproduce the bug on my machine.

   Nate


------------------------------

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End of m5-users Digest, Vol 16, Issue 7
***************************************



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