# Splash2 Run Script
#
import m5
from m5.objects import *
import os, optparse, sys
m5.AddToPath('../common')
# --------------------
# Define Command Line Options
# ====================
parser = optparse.OptionParser()
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
parser.add_option("-n", "--numcpus",
help="Number of cpus in total", type="int")
parser.add_option("-f", "--frequency",
default = "1GHz",
help="Frequency of each CPU")
parser.add_option("--l1size",
default = "32kB")
parser.add_option("--l1latency",
default = 1)
parser.add_option("--l2size",
default = "256kB")
parser.add_option("--l2latency",
default = 10)
parser.add_option("--rootdir",
help="Root directory of Splash2",
default="/dist/splash2/codes")
parser.add_option("-b", "--benchmark",
help="Splash 2 benchmark to run")
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
if not options.numcpus:
print "Specify the number of cpus with -n"
sys.exit(1)
# --------------------
# Define Splash2 Benchmarks
# ====================
class Cholesky(LiveProcess):
cwd = options.rootdir + '/kernels/cholesky'
executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\
+ options.rootdir + '/kernels/cholesky/inputs/tk23.O'
class FFT(LiveProcess):
cwd = options.rootdir + '/kernels/fft'
executable = options.rootdir + '/kernels/fft/FFT'
cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
class LU_contig(LiveProcess):
executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU'
cmd = 'LU -p' + str(options.numcpus)
cwd = options.rootdir + '/kernels/lu/contiguous_blocks'
class LU_noncontig(LiveProcess):
executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU'
cmd = 'LU -p' + str(options.numcpus)
cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks'
class Radix(LiveProcess):
executable = options.rootdir + '/kernels/radix/RADIX'
cmd = 'RADIX -n524288 -p' + str(options.numcpus)
cwd = options.rootdir + '/kernels/radix'
class Barnes(LiveProcess):
executable = options.rootdir + '/apps/barnes/BARNES'
cmd = 'BARNES'
input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus)
cwd = options.rootdir + '/apps/barnes'
class FMM(LiveProcess):
executable = options.rootdir + '/apps/fmm/FMM'
cmd = 'FMM'
if str(options.numcpus) == '1':
input = options.rootdir + '/apps/fmm/inputs/input.2048'
else:
input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus)
cwd = options.rootdir + '/apps/fmm'
class Ocean_contig(LiveProcess):
executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN'
cmd = 'OCEAN -p' + str(options.numcpus)
cwd = options.rootdir + '/apps/ocean/contiguous_partitions'
class Ocean_noncontig(LiveProcess):
executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN'
cmd = 'OCEAN -p' + str(options.numcpus)
cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions'
class Raytrace(LiveProcess):
executable = options.rootdir + '/apps/raytrace/RAYTRACE'
cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \
+ options.rootdir + '/apps/raytrace/inputs/teapot.env'
cwd = options.rootdir + '/apps/raytrace'
class Water_nsquared(LiveProcess):
executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED'
cmd = 'WATER-NSQUARED'
if options.numcpus==1:
input = options.rootdir + '/apps/water-nsquared/input'
else:
input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus)
cwd = options.rootdir + '/apps/water-nsquared'
class Water_spatial(LiveProcess):
executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL'
cmd = 'WATER-SPATIAL'
if options.numcpus==1:
input = options.rootdir + '/apps/water-spatial/input'
else:
input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus)
cwd = options.rootdir + '/apps/water-spatial'
# --------------------
# Base L1 Cache Definition
# ====================
class L1(BaseCache):
latency = options.l1latency
block_size = 64
mshrs = 12
tgts_per_mshr = 8
# ----------------------
# Base L2 Cache Definition
# ----------------------
class L2(BaseCache):
block_size = 64
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
# ----------------------
# Define the cpus
# ----------------------
busFrequency = Frequency(options.frequency)
if options.timing:
cpus = [TimingSimpleCPU(cpu_id = i,
clock=options.frequency)
for i in xrange(options.numcpus)]
elif options.detailed:
cpus = [DerivO3CPU(cpu_id = i,
clock=options.frequency)
for i in xrange(options.numcpus)]
else:
cpus = [AtomicSimpleCPU(cpu_id = i,
clock=options.frequency)
for i in xrange(options.numcpus)]
# ----------------------
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = PhysicalMemory(),
membus = Bus(clock = busFrequency))
system.toL2bus = Bus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
# Connect the L2 cache and memory together
# ----------------------
system.physmem.port = system.membus.port
system.l2.cpu_side = system.toL2bus.port
system.l2.mem_side = system.membus.port
# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
L1(size = options.l1size, assoc = 4))
cpu.mem = cpu.dcache
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2bus)
# ----------------------
# Define the root
# ----------------------
root = Root(system = system)
# --------------------
# Pick the correct Splash2 Benchmarks
# ====================
if options.benchmark == 'Cholesky':
root.workload = Cholesky()
elif options.benchmark == 'FFT':
root.workload = FFT()
elif options.benchmark == 'LUContig':
root.workload = LU_contig()
elif options.benchmark == 'LUNoncontig':
root.workload = LU_noncontig()
elif options.benchmark == 'Radix':
root.workload = Radix()
elif options.benchmark == 'Barnes':
root.workload = Barnes()
elif options.benchmark == 'FMM':
root.workload = FMM()
elif options.benchmark == 'OceanContig':
root.workload = Ocean_contig()
elif options.benchmark == 'OceanNoncontig':
root.workload = Ocean_noncontig()
elif options.benchmark == 'Raytrace':
root.workload = Raytrace()
elif options.benchmark == 'WaterNSquared':
root.workload = Water_nsquared()
elif options.benchmark == 'WaterSpatial':
root.workload = Water_spatial()
else:
panic("The --benchmark environment variable was set to something" \
+" improper.\nUse Cholesky, FFT, LUContig, LUNoncontig, Radix" \
+", Barnes, FMM, OceanContig,\nOceanNoncontig, Raytrace," \
+" WaterNSquared, or WaterSpatial\n")
# --------------------
# Assign the workload to the cpus
# ====================
for cpu in cpus:
cpu.workload = root.workload
# ----------------------
# Run the simulation
# ----------------------
if options.timing or options.detailed:
root.system.mem_mode = 'timing'
# instantiate configuration
m5.instantiate(root)
# simulate until program terminates
if options.maxtick:
exit_event = m5.simulate(options.maxtick)
else:
exit_event = m5.simulate(m5.MaxTick)
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
On Nov 15, 2007, at 12:08 PM, Sujay Phadke wrote:
Yes, it works with this array notation. Though why was it changed
from b3? I think its easier to give the arguments as a long string,
because each benchmark is using different rules to pick out the argv
values.
Some use any parameter passed without a "-" as the filename (cholesky)
In the string notation, the filename was passed like:
options.workdir + options.rootdir + '/kernels/cholesky/inputs/tk23.O
How do I write this in the array format? The concatenation doesnt
work.
- Sujay
----- Original Message ----- From: "Steve Reinhardt"
<[EMAIL PROTECTED]>
To: "M5 users mailing list" <m5-users@m5sim.org>
Sent: Thursday, November 15, 2007 4:38 AM
Subject: Re: [m5-users] sims with m5 beta4 - cache stats - any
update on this?
Good catch, thanks... but then how did it work correctly in b3? Did
that change recently?
On Nov 15, 2007 12:42 AM, Ali Saidi <[EMAIL PROTECTED]> wrote:
The args are fine, you're just passing the arguments to m5
incorrectly. The command should be an array of strings (like argv)
not
one big string. So changing the cmd line to: cmd = ['FFT', '-p',
str(options.numcpus), ' -m18'] should fix the problem.
Ali
>>>
On Nov 15, 2007, at 2:25 AM, Gabe Black wrote:
> I don't remember changing anything having to do with Alpha
process
> initialization other than the changes I made to paging, aka TLBs
in SE
> mode and everything that went with it. I don't want to say for
sure
> that
> I didn't since it was a fairly long time between b3 and b4, but I
> would
> be surprised if I did.
>
> Gabe
>
> Steve Reinhardt wrote:
>> Interesting... from what you're reporting, it sounds like the
problem
>> is likely in the code that sets up the stack (argv, argc, and all
>> that
>> good stuff). That's in LiveProcess::argsInit() in sim/
process.cc. I
>> don't know what if anything has changed in there from b3 to b4
>> though... I don't recall touching it, but Gabe might have.
>>
>> The next step would be to put a breakpoint in that function and
see
>> if
>> the argv array really does have the right number of entries,
and that
>> the entries point to the arg strings.
>>
>> Steve
>>
>> On Nov 14, 2007 10:36 PM, Sujay Phadke <[EMAIL PROTECTED]>
>> wrote:
>>
>>> A typo. In beta, the number of complex doubles reported is:
>>> 262144 Complex
>>> Doubles, which is correct since it should be 2^18. (the -m18
>>> switch passes
>>> this value).
>>>
>>> So it there some problem passing these values to the benchmarks
>>> (atleast in
>>> SE mode in beta4?) HAs something is parameter passing changed
>>> between beta 3
>>> and beta 4?
>>>
>>> ----- Original Message -----
>>> From: "Sujay Phadke" <[EMAIL PROTECTED]>
>>> To: "M5 users mailing list" <m5-users@m5sim.org>
>>>
>>> Sent: Thursday, November 15, 2007 1:29 AM
>>> Subject: Re: [m5-users] sims with m5 beta4 - cache stats - any
>>> update on
>>> this?
>>>
>>>
>>>
>>>> ok I looked at the output and I think what is happening only 1
>>>> processor
>>>> ie being assigned to the benchmark, ragardless of what value i
>>>> put. But I
>>>> dont know why this is happening. I type:
>>>>
>>>> ./build/ALPHA_SE/m5.opt configs/splash2/runsplash.py -n 4 -k
4 -b
>>>> FFT
>>>>
>>>> and still at the end of simulation using beta 4, it reports
this:
>>>> 1024 Complex Doubles
>>>> 1 Processors
>>>> 65536 Cache lines
>>>> 16 Byte line size
>>>> 4096 Bytes per page
>>>>
>>>> if I use beta3, this is what is reported:
>>>> 1024 Complex Doubles
>>>> 4 Processors
>>>> 65536 Cache lines
>>>> 16 Byte line size
>>>> 4096 Bytes per page
>>>>
>>>> the line in the config script that invokes fft is:
>>>> class FFT(LiveProcess):
>>>> cwd = options.rootdir + '/kernels/fft'
>>>> executable = options.rootdir + '/kernels/fft/FFT'
>>>> cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
>>>>
>>>> If I do a print options.numcpus here, it correctly prints out
>>>> "4". So n=4
>>>> is definitely being passed onto fft.
>>>>
>>>> I dont know why in beta 4, the correct numcpus is not being
used
>>>> by fft,
>>>> or some other benchmarks.
>>>>
>>>> Any ideas?
>>>>
>>>> Thanks for your help.
>>>>
>>>> - Sujay
>>>>
>>>>
>>>> ----- Original Message -----
>>>> From: "Steve Reinhardt" <[EMAIL PROTECTED]>
>>>> To: "M5 users mailing list" <m5-users@m5sim.org>
>>>> Sent: Thursday, November 15, 2007 12:03 AM
>>>> Subject: Re: [m5-users] sims with m5 beta4 - cache stats - any
>>>> update on
>>>> this?
>>>>
>>>>
>>>>
>>>>> I don't recall what the output files are called... each
>>>>> benchmark is a
>>>>> little different in splash. You're looking for the benchmark
>>>>> output
>>>>> in addition to the m5 output... I'm guessing something bad
>>>>> happened
>>>>> and the benchmark quit because it encountered an error.
>>>>>
>>>>> On Nov 14, 2007 4:26 PM, Sujay Phadke <[EMAIL PROTECTED]>
>>>>> wrote:
>>>>>
>>>>>> Ok. Though I dont know what to look for, since there's
nothing
>>>>>> that I
>>>>>> have
>>>>>> changed since beta3. Which output files should I examine?
>>>>>> The benchmarks ends because m5 reports "target called
exit()".
>>>>>>
>>>>>> - Sujay
>>>>>>
>>>>>> ----- Original Message -----
>>>>>> From: "Steve Reinhardt" <[EMAIL PROTECTED]>
>>>>>> To: "M5 users mailing list" <m5-users@m5sim.org>
>>>>>> Sent: Wednesday, November 14, 2007 6:31 PM
>>>>>> Subject: Re: [m5-users] sims with m5 beta4 - cache stats -
any
>>>>>> update on
>>>>>> this?
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>> Thanks, this is very interesting. Have you looked at the
>>>>>>> output from
>>>>>>> the benchmarks that are producing weird results? I'd say
from
>>>>>>> those
>>>>>>> stats (and your comment that those benchmarks are finishing
>>>>>>> "extremely
>>>>>>> fast") that the real problem is that the benchmark is
>>>>>>> terminating
>>>>>>> early, before it even gets to forking off threads on the
other
>>>>>>> CPUs,
>>>>>>> due to some error. Presumably the output is indicating
what the
>>>>>>> problem is if you look in the right place.
>>>>>>>
>>>>>>> So there's still some problem with b4 if you weren't
>>>>>>> encountering that
>>>>>>> error in b3, but it's not that the cache statistics are
broken.
>>>>>>>
>>>>>>> Steve
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> m5-users mailing list
>>>>>>> m5-users@m5sim.org
>>>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>>>>>>
>>>>>>>
>>>>>> _______________________________________________
>>>>>> m5-users mailing list
>>>>>> m5-users@m5sim.org
>>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>>>>>
>>>>>>
>>>>> _______________________________________________
>>>>> m5-users mailing list
>>>>> m5-users@m5sim.org
>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>>>>
>>>>>
>>>> _______________________________________________
>>>> m5-users mailing list
>>>> m5-users@m5sim.org
>>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>>>
>>>>
>>> _______________________________________________
>>> m5-users mailing list
>>> m5-users@m5sim.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>>
>>>
>> _______________________________________________
>> m5-users mailing list
>> m5-users@m5sim.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>>
>
> _______________________________________________
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> m5-users@m5sim.org
> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>
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