You could certainly build this configuration, but the coherence protocol will not work transparently across the bus bridge. You'd have to adapt the coherence protocol and/or the bridge to make it work (just like in the real world).
Steve On Dec 14, 2007 1:19 PM, Shoaib Akram <[EMAIL PROTECTED]> wrote: > I want to simulate the following system: > > A total of four cores each with L1 private L1 caches. Two cores connected by > a shared bus. The other two cores also connected by a shared bus. The two > clusters connected together by a point to point link or something. > > In essence, the goal is to have two separate shared bus fabrics in the system. > > Any idea how to model this in m5. I know m5 has this bridge mechanism but has > anybody used it successfully? > > Regards, > Shoaib > _______________________________________________ > m5-users mailing list > m5-users@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
