Normally I add a -s to that command line because I want to create
checkpoints with the atomic cpu, I restore from the checkpoints
immediately into the timing cpu where the caches are warmed up and
then I switch to a detailed cpu model. The -w flag has no meaning
unless the -s (standard switch) flag is used.
You'll need to modify the scripts a little bit if you want to do
anything else. If you want to just transition into a timing cpu and
not into a detailed cpu you'll need to change line 64 in Simulation.py
from root.switch_cpus = switch_cpus to
testsys.switch_cpus = switch_cpus and then add some code to alter the
atomic warm up period. Alternatively you could use the standard switch
code and change the O3 cpu to another timing cpu if you wanted to end
up with a simple cpu model that would allow statistics to be collected
on the other cpu after the switch over.
Ali
On Dec 17, 2007, at 6:49 AM, abc def wrote:
I tried using following command line:
build/ALPHA_FS/m5.opt configs/example/fs.py -n 4 -r 1
--timing --caches -w 50000000000, so that it switches
to timing simple cpu only after warming up caches with
atomic simple cpu.
But nothing is happening in console. It is not getting
restored from checkpoint.
I am using system files from version b3.
Can you please forward me the command line you use
for booting up timing simple cpu.
--- Ali Saidi <[EMAIL PROTECTED]> escribió:
It's another bug, but since we never really boot
with timing and
caches it's not surprising that we haven't seen it
before.
Ali
On Dec 16, 2007, at 11:43 PM, Nathan Binkert wrote:
This could honestly be just because it takes a
long time. With
timing and caches, the simulator is pretty slow.
This is working if caches option is not used.
But with L1,L2 cache present and with multiple
cpus it
is still getting stuck while booting.
command line used:
build/ALPHA_FS/m5.opt configs/example/fs.py -n 4
--timing --caches --l2cache
--- Ali Saidi <[EMAIL PROTECTED]> escribió:
There is an issue in b4 with when the CPU ids
get
assigned to CPUs
that can cause some weird behavior in all
multi-processor
configurations (2,3,4, xxx cpus). The attach
patch
fixes those problems.
Ali
On Dec 16, 2007, at 2:53 AM, Ali Saidi wrote:
Yea, you found a bug. I found the changeset
that
caused the problem,
and I'll try to figure out what is going on
tomorrow and post a patch.
In the future please create a new topic on the
mailing list by
sending a new message to m5-users@m5sim.org
instead of replying to a
current topic and changing the subject.
Replying
to the same topic
and just changing the subject preserves the
In-Reply-To mail header
and makes it more difficult to reconstruct
threads
of conversation
on the mailing list.
Ali
On Dec 15, 2007, at 7:57 PM, abc def wrote:
Timing simple cpu in full system mode in m5
beta
4 is
not booting up. In the console it is getting
stuck
into "NET: Registered protocol family 2" and
is
not
proceeding forward.
System files are from:
http://www.m5sim.org/dist/current/m5_system_2.0b3.tar.bz2
This is happening if 4 cpus are used for
booting.
For
1 cpu it is ok.
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