[m5-users] Simulating heterogeneous multicore processors

[Alexandra (Sasha) Fedorova]

Can M5 be configured to simulated heterogeneous multicore processors? For 
example, can I have a configuration where one core is OOO, one core is 
scalar in-order? Similarly, can I configure cores with different CPU 
frequencies, different cache sizes, different number of functional units?

-- Sasha
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