On Feb 13, 2008, at 5:26 PM, Rick Strong wrote:
Hi all,
Background:
I would like to analyze the cold start effects of migrating a thread
between two cpus by periodically jumping out of the simulate
routine, writing all the caches (L1+L2) out to memory, and clearing
the processor state (branch history tables, tlb entries, etc) and
having the thread start in this cold state. By doing this cold start
N times over a 100M instruction sample and looking at the average
increase in execution time, this would give me the cold start
effects of migration and I could just add a number of cycles for
migrating ISA state (registers mostly) between two cores.
Questions:
1)What does m5.drain(testsys) do, as it is not obvious after diving
in the code for a while and can it be used for clearing cache state?
It tells all the SimObjects to stop issuing requests and executes a
few cycles until all memory requests complete and their responses make
it back to the initiating SimObject. It doesn't clear the cache state
(in fact nothing we have written does). Do do that you could drain and
then have the cache issue functional memory requests to write back all
the dirty data and clear the tags.
2)Does anyone have an existing methodology for getting thread
migration delay (between cores) in m5?
Not that I know of....
3)If no for 2, would anyone be interested in having support to find
this delay?
-Rick
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