Hi Mike Nice to hear you now are able to compile.
First: The DE10_Nano_SoC_DB25 project is setup so it can be loaded directly in Quartus and compile out of the box, as a convinience. Online packed and built bitfiles follow the Docker build method (in quartus 15) via running the build.sh script. https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE0_Nano_SoC_DB25/build.sh hostmot2_cfg.vhd <https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE10_Nano_SoC_FB_DB25/hostmot2_cfg.vhd> is just a renamed copy of: "hostmot2_cfg.vhd.in" https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE0_Nano_SoC_DB25/hostmot2_cfg.vhd.in Notice that the DE10/DE0 .._DB25 share the same hm2 config folder: https://github.com/machinekit/mksocfpga/tree/master/HW/hm2/config/DE0_Nano_SoC_DB25 the hostmot2_cfg.vhd.in file should probably have been moved to this folder and that folder renamed to DEx_Nano_SoC_DB25 When the DE10 nano port was added for more clairity...... Second: About adding a HM2 DRO core to qsys for: > Magnetic Resolvers ... used for the Digital Readout for the LinuxCNC > ahrmm Machinekit ... The MkSoc platform is based upon ported Mesa vhdl cores, and communicate through a memorymapped uio port via the hm2_soc_ol driver: https://github.com/machinekit/machinekit/blob/master/src/hal/drivers/mesa-hostmot2/hm2_soc_ol.c For the hal system to be able to "see" any added functionality without writing a new driver it has to be on the "other side" of the hm2 uio port, ie. in the hostmot 2 memory map somewhere around here: https://github.com/machinekit/mksocfpga/blob/master/HW/hm2/hostmot2.vhd Anyway I suggest first look at the Mesa2 core docs in Linuxcnc and machinekit and sede if there is something allready/allmost providing the functionality you seek to add and use that as a starting point, .... Best wishes Michael On Wednesday, 1 August 2018 04:20:22 UTC+2, mike Kennedy wrote: > > Solved?? > > Ok I dug more into it and Found a few things. > > First of all, My Python was getting confused between the 2 different > versions. Python2.7 and Python3.5. > the protobuf protocols we not installed for the Python2.7 version. but was > for 3.5. > I solved this by installing protobuf with "python -m pip install protobuf" > > Second issue. > > I did notice that when I ran the ./build.sh script the file " > hostmot2_cfg.vhd.in" was missing from the DE0_Nano_Soc_DB25 directory. > Not sure why. > > I then just copied it from the DE10 directory and seems to be working now!. > > Thanks. > MikeK > > > cp hostmot2_cfg.vhd.in ../DE0_Nano_SoC_DB25/ > > > > > On Tuesday, July 31, 2018 at 6:10:23 PM UTC-4, mike Kennedy wrote: >> >> Hi Guys: >> >> New to the forum here, and still learning "machinekit/mksocfpga" So >> please bare with me. >> System is Ubuntu 16.04 with Altera Quartus version 18.0 >> >> I recently have tried to build the FPGA core for the DE0_Nano_Soc_DB25. >> The the following is the output from the build script here located in: >> mksocfpga <https://github.com/machinekit/mksocfpga>/HW >> <https://github.com/machinekit/mksocfpga/tree/master/HW>/ >> *README.BuildSystem.txt* at step "make rbf" >> >> Here is the output I get for the following error message: >> >> Info (12021): Found 1 design units, including 1 entities, in source file >> soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v >> Info (12023): Found entity 1: altera_std_synchronizer_nocut File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system/synthesis/submodules/altera_std_synchronizer_nocut.v >> >> Line: 44 >> Info (12021): Found 1 design units, including 1 entities, in source file >> soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v >> Info (12023): Found entity 1: altera_avalon_st_idle_remover File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v >> >> Line: 19 >> Info (12021): Found 1 design units, including 1 entities, in source file >> soc_system/synthesis/submodules/altera_avalon_st_idle_inserter.v >> Info (12023): Found entity 1: altera_avalon_st_idle_inserter File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system/synthesis/submodules/altera_avalon_st_idle_inserter.v >> >> Line: 19 >> Info (12021): Found 1 design units, including 1 entities, in source file >> soc_system/synthesis/submodules/soc_system_dipsw_pio.v >> Info (12023): Found entity 1: soc_system_dipsw_pio File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system/synthesis/submodules/soc_system_dipsw_pio.v >> >> Line: 21 >> Info (12021): Found 1 design units, including 1 entities, in source file >> soc_system/synthesis/submodules/soc_system_button_pio.v >> Info (12023): Found entity 1: soc_system_button_pio File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system/synthesis/submodules/soc_system_button_pio.v >> >> Line: 21 >> Info (12021): Found 2 design units, including 1 entities, in source file >> DE0_Nano_SoC_DB25.vhd >> Info (12022): Found design unit 1: DE0_Nano_SoC_DB25-arch File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd >> >> Line: 121 >> Info (12023): Found entity 1: DE0_Nano_SoC_DB25 File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd >> >> Line: 40 >> Error (10481): VHDL Use Clause error at DE0_Nano_SoC_DB25.vhd(355): >> design library "work" does not contain primary unit "HostMot2_cfg". Verify >> that the primary unit exists in the library and has been successfully >> compiled. File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/DE0_Nano_SoC_DB25.vhd >> >> Line: 355 >> Warning (10236): Verilog HDL Implicit Net warning at >> altera_edge_detector.v(21): created implicit net for "reset_qual_n" File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/cv-ip/edge_detect/altera_edge_detector.v >> >> Line: 21 >> Warning (10236): Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): >> created implicit net for "pll_dr_clk" File: >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/soc_system/synthesis/submodules/ >> hps_sdram_pll.sv Line: 168 >> Info (144001): Generated suppressed messages file >> /home/mikek/Documents/Mike_Play_Learn/CAM/mksocfpga/HW/QuartusProjects/DE0_Nano_SoC_DB25/output_files/DE0_Nano_SoC_DB25.map.smsg >> Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 4 >> warnings >> Error: Peak virtual memory: 1056 megabytes >> Error: Processing ended: Tue Jul 31 17:35:50 2018 >> Error: Elapsed time: 00:03:53 >> Error: Total CPU time (on all processors): 00:04:13 >> Makefile:210: recipe for target 'stamp/quartus_pin_assignments.stamp' >> failed >> make: *** [stamp/quartus_pin_assignments.stamp] Error 3 >> >> >> This is the Quartus Map stage, After the QSYS reconfigure has completed >> correctly (From what I can tell) >> >> I did notice that the during the elaboration stage Quartus could not find >> file *hostmot2_cfg.vhd* -- "Warning (12019): Can't analyze file -- file >> hostmot2_cfg.vhd is missing" >> Is there another procedure here to create this config file or copy it >> from another location? >> >> Thanks for all your help! >> >> ---Side Note--- >> >> The reason I would like to compile the FPGA code from scratch. I am >> working on writing custom Verilog code for the Magnetic Resolvers that I >> have on my Milling Machine. >> This will then be used for the Digital Readout for the LinuxCNC. This is >> the plan. The inner workings of machinekit I am still unfamiliar with. >> But at some point, A HDL based DRO generated register access would be >> available to the HPS system within QSYS. >> >> This is the plan anyway, Any insight of the usefulness of this would be >> greatly encouraged. >> >> Mike Kennedy. >> > -- website: http://www.machinekit.io blog: http://blog.machinekit.io github: https://github.com/machinekit --- You received this message because you are subscribed to the Google Groups "Machinekit" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. Visit this group at https://groups.google.com/group/machinekit. For more options, visit https://groups.google.com/d/optout.
