Thanks Michael! Some little news about my project: I am working in myHDL (yep, python) and I am using this repo https://github.com/mngr0/test myHDL gets translated in verilog or VHDL before synthesis, I go for verilog, to use icestorm. (I am learning a lot in these days). At this point I have a very simple pulse generator, with some other support module (or block, depending on the language you are used to) All the motor control side is overall easy to implement, but I have problem to understand how machinekit/linuxcnc communicate with the mesa card (can I say that there is a protocol, and call it hostmot2?) I have been told to look in hal/drivers/mesa-hostmot2 <https://github.com/LinuxCNC/linuxcnc/tree/master/src/hal/drivers/mesa-hostmot2> in linuxcnc repo, or in the VHDL source code, but there is a very lot of code, and I don't even exactly know what I am looking for... can anyone bring some light on this?
mngr0 Il giorno giovedì 2 agosto 2018 14:52:41 UTC+2, Michael Brown ha scritto: > > THe hostmot3 variant has been tied to the (neglected)Cramps cape versions, > and > an experimental persuit to create a more comprehensive Systemverilog > config system. > > The simplicity is due only including stuff that can be driven by the (bbb) > Cramps cape: > steppers, pwm's and adc converter. > > I think the xxx_Cramps projects still are in working shape and should be > more easy to comprehend > due to the minimal functionality. > > BTW > Nice to hear from a fellow Verilog programmer :-) > > On Saturday, 28 July 2018 16:15:50 UTC+2, mngr wrote: >> >> I just realized that hostmot3 does the same thing of hstmot2, but the 3 >> is very more tidy. >> I was following the signals to and form the modules (the entityes used in >> hostmot3) and i see that they come from outside of hostmot3. >> Then I saw the hostmot3_cfg.vhd file in DE0 and DE10 config folders, but >> here too the signals come from outside... >> I think that the "main" is generated by a script >> >> >> >> Il giorno venerdì 27 luglio 2018 17:06:23 UTC+2, mngr ha scritto: >>> >>> thanks pcwcol, >>> >>> the index/probe support has some concrete functionality or is only for >>> debugging? >>> >>> I see hostmot2 and hostmot3, can I assume that these are two possible >>> global configuration (I mean, they are never used togheter)? >>> a grep reveals that hostmot3 does not make use of any stepgen entity, so >>> I am ignoring it. >>> >>> Is this right or I am missing something? >>> - mostra testo citato - >>> >>> >>> Il giorno mercoledì 18 luglio 2018 19:40:37 UTC+2, pcwcol ha scritto: >>>> >>>> >>>> >>>> On Tuesday, July 17, 2018 at 7:55:08 AM UTC-7, mngr wrote: >>>>> >>>>> Thanks Charles, >>>>> >>>>> The open source toochain for Lattice FPGA works only with Verilog, for >>>>> what I know, so I will have to translate from VHDL. >>>>> What do you think about that? >>>>> >>>>> I have tried to understand wat the qcounter* modules do, but may I ask >>>>> for a bit of explanation about them? >>>>> >>>>> What other modules do I need to make a step generator? (the most >>>>> simple possible) >>>>> what is the difference between kubstepgenz and kubstepgenzi? (I guess >>>>> those are stepgens... what does the "i" stands for? just like "kub", what >>>>> does it mean?) >>>>> >>>>> >>>>> Thanks and regards, >>>>> mngr >>>>> >>>>> Il giorno sabato 9 giugno 2018 03:52:01 UTC+2, Charles Steinkuehler ha >>>>> scritto: >>>>>> >>>>>> On 6/7/2018 11:46 AM, mngr wrote: >>>>>> > Hi everybody, >>>>>> > >>>>>> > I am trying to replicate the mesa drivers, but using a Lattice >>>>>> FPGA, since >>>>>> > there is an open source toolchain for them. >>>>>> > I want to do something like the 7i76, maybe 7i76E if managing the >>>>>> ethernet >>>>>> > does not consume too much logic elements. >>>>>> > >>>>>> > I have seen mksocfpga, and I have searched for a vhd module that >>>>>> control >>>>>> > the position and gives steps and direction to the motor. >>>>>> > Is there a module like that? >>>>>> >>>>>> Yes, see the qcounter*.vhd files: >>>>>> >>>>>> https://github.com/machinekit/mksocfpga/tree/master/HW/hm2 >>>>>> >>>>>> > My idea for a first implementation is to use a Raspberry with an >>>>>> ico-Board >>>>>> > on top of it, and connect them via SPI, what do you think about it? >>>>>> >>>>>> I'd start with the VHDL source for one of the SPI connected Mesa >>>>>> boards (like the 7i90) and try to get that to compile on the Lattice >>>>>> parts. If you don't understand some of the HDL code (even if you >>>>>> know >>>>>> VHDL, it can be kind of confusing the way it's instantiated), just >>>>>> ask >>>>>> your questions here. There are a couple of folks here familiar with >>>>>> the hm2 VHDL source. >>>>>> >>>>>> -- >>>>>> Charles Steinkuehler >>>>>> [email protected] >>>>> >>>>> >>>> >>>> kubstepgen = john Kasunich UnBuffered stepgen (since the basic stepgen >>>> architecture is patterned after Johns software stepgen component) >>>> >>>> kubstepgeni = version with index/probe support (latch stepgen count at >>>> index or probe event) >>>> >>>> -- website: http://www.machinekit.io blog: http://blog.machinekit.io github: https://github.com/machinekit --- You received this message because you are subscribed to the Google Groups "Machinekit" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. Visit this group at https://groups.google.com/group/machinekit. For more options, visit https://groups.google.com/d/optout.
