I have now put the 2 PR's in here:
https://github.com/machinekit/machinekit-hal/pull/213
https://github.com/machinekit/mksocfpga/pull/106

On Friday, 31 May 2019 02:29:04 UTC+2, Michael Brown wrote:
>
> MK-Hal:
> I expect the answer to be no as while implementing this functionality on 
> the mksocfpoga DExx_Cramps I had to iron out some noticable bugs:
> I expect to upstream these changes soon (in machinekit-hal), however they 
> will probably
> break any (work arounded) exsisting implementations, that will need to be 
> updated:
> https://github.com/the-snowwhite/machinekit-hal/commits/fix_hm2-spi
>
> Also I added support for the buffered spi's with decoded chip selects 
> (dbspi). (tested to work ok)
>
> MkSoCFPGA:
> Lastly I had a problem with 3 spi messages being send instead of one:
> The issue here relates to All quartus based mksocfpga configs:
> as the uio port was set to clock out data for 2+ cycles to the hm2 cores.
> This meant that all data writes to the hm2 cores where trippled,(not a 
> huge issue for the cores used up to date)
>  first notacable via the bspi cores that then sent same message 2 times 
> more when write triggered.
>
> So here is the nessesary Global change, of the write timing:
>
> https://github.com/the-snowwhite/mksocfpga/commit/b988a7b7218fd1b8b5664d84436ddc6efca4c025#diff-866caa37e2c4e9882a0a92a9672af4ceR147
>
> Everything is tested on my (3) DExx_Cramps based machines, and all works 
> fine here,,, 
>
> Best wishes
> Michael B.
>

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