On Saturday, July 18, 2020 at 4:06:45 PM UTC-7, Cameron McQuinn wrote: > > Hi all, > > I am looking to gain a better understanding of how the clocking for the > Hostmot2 firmware works in mksocfpga. In the Vivado block diagram, the > hostmot2_ip_wrap module has 3 clock ports: clklow, clkmed, and clkhigh. The > TCL scripts to generate the Vivado projects all connect clklow and clkmed > together. Clkmed and clklow connect to a 100MHz clock, and clkhigh connects > to a 200MHz clock. Where did these numbers come from? > > Also, in the PIN_XXXXX file for each configuration, each module has an > associated clock tag. For instance, in PIN_ULTR_36.vhd, the PWM module has > the ClockHighTag ( > https://github.com/machinekit/mksocfpga/blob/master/HW/VivadoProjects/avnet/ultra96/const/PIN_ULTR_36.vhd#L83). > > Is there some place in the HM2 code that defines what clock tag each module > should have? > > Thanks, > Cameron >
Not sure about mksocfpga but in general the clocking setup is pretty simple, the top level (card specific) file generates the various clocks from the clock source ( via DCM, PLL etc depending on hardware) These are simple fixed hardwired frequencies for a given card. Card specific constants (on IDROMConst.vhd) are used to simply pass the fixed hardware clock frequencies to the hm2 driver for its frequency based calculations The clock tags that specify which clock a module uses (for determining I/O frequencies) is in the module ID section of the pinout file:PINXXXX. vhd -- website: http://www.machinekit.io blog: http://blog.machinekit.io github: https://github.com/machinekit --- You received this message because you are subscribed to the Google Groups "Machinekit" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/machinekit/4f2f931c-5121-45aa-87d8-64e617c9007ao%40googlegroups.com.
