Here is a complete debug info:

MemoryController (this=0x2e75750, coreid=<value optimized out>, name=0x7fffffffd120 "MEM_0", memoryHierarchy=0x2adca60) at ptlsim/build/cache/memoryController.cpp:50
50        memoryHierarchy_->add_cache_mem_controller(this);
(gdb)
52 if(!memoryHierarchy_->get_machine().get_option(name, "latency", latency_)) {
(gdb)
57        latency_ = ns_to_simcycles(latency_);
(gdb)
59 SET_SIGNAL_CB(name, "_Access_Completed", accessCompleted_, &MemoryController::access_completed_cb);
(gdb)
[Thread 0x7ffebb36b950 (LWP 6858) exited]
61 SET_SIGNAL_CB(name, "_Wait_Interconnect", waitInterconnect_, &MemoryController::wait_interconnect_cb);
(gdb) print &accessCompleted_
$3 = (superstl::Signal *) 0x2e75ad0
(gdb) print &waitInterconnect_
$4 = (superstl::Signal *) 0x2e75bf0

(gdb) print *queueEntry
$7 = {<FixStateListObject> = {<superstl::selfqueuelink> = {_vptr.selfqueuelink = 0x800800, next = 0x2e75d48, prev = 0x2e76b58}, idx = 0, free = false}, request = 0x2adcba8, source = 0x0, depends = -1, annuled = false, inUse = true}
(gdb) print &accessCompleted_
Cannot access memory at address 0x1f8

Hello,

I am trying to add my memory simulation in marss. What I did is to pass the request to my memory simulation part in MemoryController::handle_interconnect_cb() and after the request is finished, the memory simulation will call memoryHierarchy->add_event(&accessCompleted_, 1, queueEntry);

In my codes, I got a segmentation fault which confused me a long time. Here is what I see:

each time when memoryHierarchy->add_event(&accessCompleted_, 1, queueEntry) is called, there is segmentation fault.

I use gdb to print *queueEntry and am sure queueEntry is fine. But when I print &accessCompleted_, it says:
Cannot access memory at address 0x2a

I went back to the constructor,  and print &accessCompleted_, it says:
(gdb) print &accessCompleted_
$3 = (superstl::Signal *) 0x2e66640

So I am confused how the &accessCompleted_ changes? Could you please help me out? I really appreciate.

Thanks and regards,

Kuniors



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