Hi, I recently look into Marss86 for university project. Want to extend cache coherence mechanism and make it look like AMD opteron system. Is possible?
I read code, MOESI cache coherence function and have some question: - handle_cache_insert called BEFORE insert and track eviction of old line, correct? - complete_request used for actual insert I believe - Why is there handle_cache_evict? Sometimes assert(0) only content. - Real (old) AMD systems not have directory (probe filter), but still MOESI. Can have the same thing in Marss? Or directory always needed in MOESI? Why? Or L3 also implicit directory? - Local write hit to O / E / S line, line invalidated and request handled in lower interface? Why? Inclusive cache mandate? Write-through cache? - Eviction logic there twice? In handle_cache_insert and handle_local_hit? Maybe misunderstanding everything. - interconnect_hit not going to upper interface? Must probe away all lines there, too, right? - Never any victim / fill from inner (e.g. L1) to outer (L2) cache because inclusive hierarchy. Can always invalid line, right? Can have more detail (line number, file) if you think helpful. Maybe good tutorial I can read? Thank you, Alexey
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