Hi There
I have been looking into AMD Opteron 16 Core architecture and was wondering how
to simulate its cache configuration in MARSS86. The details of which are:
L1 Cache: 16KB/core + 64KB instruction/module (i.e. 2 cores per module)
L2 Cache: 1MB (per core)
L3 Cache: 16MB (per socket)(i.e. 16 core, or 8 modules per socket)
How can I have L1-I Cache that is shared among a core pair, L1-D Cache and L2
Cache that is dedicated for each core? Any help in scripting that would be
highly appreciated.
Regards
Yasir
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