On Wednesday 17 October 2012, 17:49:10 Huang Lianjun wrote: > If there are two or more L2 cache miss outstanding, their counters > mb.cycles decrease by 1 cycle in every loop.It means that transfering > data from L2 cache to L1 cache happens and data are read from > different addresses of L2 cache and written into different addresses > of L1 cache simultaneously. How is this possible ?
You are right. Contention in the outer caches is not prperly modelled in PTLsim. For that you really would want to check the Marss86 simulator that has queues etc. in the caches. Stephan > > Thank you! > > 2012-10-17 > > > > Huang Lianjun > > > > 发件人：Stephan Diestelhorst > 发送时间：2012-10-16 22:50 > 主题：Re: [PTLsim-devel] how parallel access to memory happens > 收件人："ptlsim-devel"<[email protected]> > 抄送："hljhnu"<[email protected]>,"marss86-devel"<[email protected]> > > On Sunday 30 September 2012, 11:06:32 hljhnu wrote: > > Hi,everyone, > > I am performing research work on PCM using PTLsim. I find that there > > is a loop inside the function void MissBuffer::clock() in the file > > dcache.cpp. It implies that parallel access to memory or caches > > happens. But how can it happen with only a memory rank. In addition, > > the number of Level-1 D-cache has only 8 banks while the size of > > MissBuffer is 64. > > The L1d accesses are not handled by the MissBuffer. Traditionally, L1d > is more considered part of the core. Bank conflicts in L1d are checked > in ReorderBufferEntry::issueload in oooexec.cpp. Marss has changed > that IIRC. > > > So the banks cannot explain the parallel access. I get confused. > > The idea is to handle multiple in flight memory requests and advance > their state machines properly. The size of the MIssBuffer just > indicates, how many memory requests you can have outstanding to the > MemoryHierarchy. Note that the memory hierarchy is non-blocking, and > there can be multiple misses in flight. > > > If I want to add some function such as record the write-memeory time, > > how can I do it ? > > What is the write memory time? Time from retire of the store to the > data turns up in the cache? The store is removed from the memory > hierarchy? There is a problem at least with PTLsim in that stores are > essentially fire-and-forget from the CPUs perspective. They retire and > fire off their request to the MissBuffer and never check that the > request actually completes. You might add the tracking in the clock > function of the miss buffer, i.e., memorise the time when you add the > request and compute the difference when it finishes processing in there. > > Stephan > > > > Huang Lianjun > > 2012-09-30 > -- > Stephan Diestelhorst, AMD Operating System Research Center > [email protected] > Tel. +49 (0)351 448 356 719 > > Advanced Micro Devices GmbH > Einsteinring 24 > 85609 Aschheim > Germany > Geschaeftsfuehrer: Alberto Bozzo u. Andrew Bowd > Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen > Registergericht Muenchen, HRB Nr. 43632, WEEE-Reg-Nr: DE 12919551 -- Stephan Diestelhorst, AMD Operating System Research Center [email protected] Tel. +49 (0)351 448 356 719 Advanced Micro Devices GmbH Einsteinring 24 85609 Aschheim Germany Geschaeftsfuehrer: Alberto Bozzo u. Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632, WEEE-Reg-Nr: DE 12919551 _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
