Hi,
i am sorry, but there is no such ifdef. The code has been changed to automatically 
detect (via CPUID) if it is possible to use 'sfence' (store fence AKA write memory 
barrier) instead of 'lock cmpxchg' for unlocking. This result is stored internally 
since it is expected, that the CPU type does not change while the kernel is running 
;-) 
This makes the assembler coding somewhat more complicated. In addition to this, the 
RTESys_MemoryBarrier.s was added due to problems with aggressive instruction 
reordering on Multi CPU PowerPC4 architectures (AIX), Multi CPU Itanium Architecture 
(proven on Linux, maybe on Itanium...) and (not yet proven to be a problem) on Multi 
CPU Pentium4 and newer Multi CPU Pentium3 (Xeons) (Linux/Windows). Therefore it was 
absolutely necessary to add Memory Barrier
support. On those platforms, that do not provide 'system header internals...' to allow 
to specify a memory barrier, the additional assembler code is needed.

You could remove CPU detection on Solaris/x86 in RTESys_AsmSpinlock.s only, if you 
modify the RTESys_MemoryBarrier.s too...


Here is an untested castrated version for conservative Intel code... It wont reach the 
same performance as memory barrier instructions but will be save...

Modification on RTESys_MemoryBarrier.s needed:

&if  $ASCOMMENT
;-------------------------------------------------------------------------
&endif

&if  $MACH = I386 and $OSSPEC = LINUX
    .file       "RTESys_MemoryBarrier.s"
    .text

&ifdef IGNORE_CPU_TYPE
    .globl  RTESys_WriteMemoryBarrier
    .align  4
RTESys_WriteMemoryBarrier:
    lock
    addl    $0,(%esp)
    ret

    .globl  RTESys_ReadMemoryBarrier
    .align  4
RTESys_ReadMemoryBarrier:
    lock
    addl    $0,(%esp)
    ret

    .globl  RTESys_MemoryBarrier
    .align  4
RTESys_MemoryBarrier:
    lock
    addl    $0,(%esp)
    ret
&else
    .globl  RTESys_WriteMemoryBarrier
    .align  4
RTESys_WriteMemoryBarrier:
    testb   $0xff,RTESys_i386CPUType   # get RTESys_i386CPUType with family
    jne     _dont_get_cpu_type_wmb  # GetCPUType already called?
    call    _GetCPUType
_dont_get_cpu_type_wmb:

    mov     RTESys_i386FeaturesEDX,%edx
    bt      $25,%edx                # Feature Flags Bit 25 is SSE support
    jc      _sse_or_sse2_supported  # jump if SSE is supported

    lock
    addl    $0,(%esp)
    ret

_sse_or_sse2_supported:
    sfence
    ret

...
...
...
&endif

Modification on RTESys_AsmSpinlock.s needed:

&if $OSSPEC = LINUX AND $MACH = I386
        .file  "RTESys_AsmSpinlock.s"
&ifdef IGNORE_CPU_TYPE
        .align  4
          .text
        .globl  RTESys_AsmTestAndLock
        .type   RTESys_AsmTestAndLock,@function
RTESys_AsmTestAndLock:
        movl    4(%esp),%edx            # get (* addr)
        movl    (%edx), %eax            # get the current lock value
        movl    $1, %ecx                # set the intended lock value

_lock_again:
        lock
        cmpxchg %ecx,(%edx)
          jne     _lock_again
          ret

        .globl  RTESys_AsmUnlock
        .align  4
          .type   RTESys_AsmUnlock,@function
RTESys_AsmUnlock:
        movl    4(%esp),%edx            # get (* addr)
        movl    (%edx), %eax            # get the current lock value
        xorl    %ecx,%ecx               # set the intended unlock value

_unlock_again:
        lock
        cmpxchg %ecx,(%edx)
          jne     _unlock_again                 # loop until no collision detected

          ret
&else
        .data
            .globl  RTESys_i386CPUType
                .globl  RTESys_i386VendorID
                .globl  RTESys_i386CPUSignature
            .globl  RTESys_i386FeaturesEDX
            .align  4
RTESys_i386VendorID:     .byte '-','-','-','-','-','-','-','-','-','-','-','-',0
RTESys_i386CPUType:      .byte 0
                .align  4
RTESys_i386CPUSignature: .int 0
RTESys_i386FeaturesEDX:  .int 0

            .text
                .globl  _GetCPUType
            .align  4
_GetCPUType:
# Execute CPUID instruction to determine vendor, family,
# model, stepping and features. For the purpose of this
# code, only the initial set of CPUID information is saved.

             push   %ebx    ################ save registers

                 mov    $0,%eax         # set up for CPUID instruction
             cpuid                  # get and save vendor ID
                 mov    %ebx,RTESys_i386VendorID
             mov    %edx,RTESys_i386VendorID+4
                 mov    %ecx,RTESys_i386VendorID+8
             cmpl   $1,%eax         # make sure 1 is valid input for CPUID
                 jl     _end_cpuid_type # if not, jump to end

             mov    $1,%eax
...
...
...
&endif


Hope this helps you Solaris/X86 efforts.
CU
jrg

> -----Original Message-----
> From: "D�hr, Markus ICC-H" [mailto:[EMAIL PROTECTED]
> Sent: Donnerstag, 10. Juni 2004 03:09
> To: '[EMAIL PROTECTED]'
> Subject: Solaris/x86: RTESys_AsmSpinlock.s 
> 
> 
> Hi,
> 
> trying again to create a new unified diff against the actual 
> tree (maxdb-75)
> but I have big trouble compiling
> sys/src/SAPDB/Runtime/System/RTESys_AsmSpinlock.s
> 
> There were some recent changes in this file which do not 
> compile anymore.
> 
> The Solaris assembler is somewhat different from the gnu assembler. I
> haven't yet found a way to 
> 
> - make it compile with Solaris' as
> - revert the changes so that the "old" version is used (if possible)
> - customize the build environment so that only this file is 
> compiled using
> gnu as.
> 
> The latter seems to be the easiest way but trying back and 
> forth I'm still
> not able to do this myself.
> 
> Any pointer where to "&ifdef"?
> 
> 
> Thanks very much!
> 
> 
> 
> SIEGENIA-AUBI KG
> Informationswesen
>  
> i.A.
>  
> Markus D�hr
> SAP-CC/BC, SAPDB-DBA
> 
> Tel.:  +49 6503 917-152
> Fax:   +49 6503 917-7152
> E-Mail: [EMAIL PROTECTED]
> Internet: http://www.siegenia-aubi.com 
>  
> 
> -- 
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