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Let me know if you have any consultants with the following skills Job : ASIC Physical Design Engineer Location : Dallas, TX or Austin, TX (your choice) Duration : 9+ Months Here are the minimum requirements: a.. ASIC Physical design experience of at least 5 - 7 years. b.. Cadence Encounter tool experience of at least 2+ years. c.. Cadence Encounter RTL to GDS flow experience of at least 1+ years. d.. Good PrimeTime STA experience. e.. Has worked on 45 nm ASIC designs (this is a MUST) nm stands for nanometer. This is submicron development. f.. Has worked on ASIC with performance or speed running at 1 Ghz (gigahertz) -- or greater. This is a must. g.. Nice to have some type of data path or similar background but not required. Position: ASIC Physical Design Engineer Job Description: Support senior unit owners in Physical Design activities including but not limited to: Synthesis, P&R, STA, DRC/LVS cleanup Skills or expertise required: a.. RTL 2 GDSII Implementation - Synthesis, P&R, STA, Equivalence Checking, DRC/LVS, Power/Reliability Analysis b.. Cadence tool (RTL-Compiler & EDI) knowledge a must c.. Strong logic design knowledge Prior experience required: a.. High-performance processor design b.. Good understanding of deep-submicron (28nm/32nn/45nm) issues c.. Scripting knowledge (TCL/PERL/Makefile) Prior experience that would be helpful or nice to have: a.. Logic Design & Structured Datapath or Tiling b.. Power management techniques (multiple power/voltage domains) c.. Good at logic equivalence checks (preferably Conformal LEC) Level of expertise required: a.. Execute a well-defined task Thanks & Regards, Nagesh, Zip Logic LLC. Ph: 510-250-7616, FAX: 510-578-1309 Email: [email protected], -- You received this message because you are subscribed to the Google Groups "MCMS" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/mcms?hl=en.
