To be precise, each socket has 3 16x line. The others (1x, 2x, 4x, 8x) goes 
through the PCH before reaching the CPU, as usual.
"lspci -tv" to view the pci topology.

On Thursday, May 25, 2017 at 7:58:00 AM UTC+2, Wojciech Kudla wrote:
>
> > Since Sandy Bridge at least, each CPU has
> its own PCIe interface. Presumably, if you're doing user-space kernel 
> bypass IO you want your workload on the same CPU that your IO devices are 
> connected to.
>
> I think you meant the whole socket here. Yes, this is one of the reasons 
> why many shops move away from 4-socket rigs as it sometimes gets really 
> challenging to partition PCIe/cpu/memory resources when running multiple 
> latency critical processes. 
>
> On Thu, 25 May 2017, 00:49 Ross Bencina, <[email protected] 
> <javascript:>> wrote:
>
>> On 22/05/2017 5:47 PM, Himanshu Sharma wrote:
>> > Did you find a satisfactory reason for not isolating cpu 0, maybe some
>> > low level OS code that is bound to run on core 0?
>>
>> Throwing this out there for comment:
>>
>> In addition to Linux kernel internals, you might want to consider which
>> CPU your IO is connected to. Since Sandy Bridge at least, each CPU has
>> its own PCIe interface. Presumably, if you're doing user-space kernel
>> bypass IO you want your workload on the same CPU that your IO devices
>> are connected to. Otherwise you want the kernel running on the CPU that
>> is directly connected to IO.
>>
>> Or you could work out the CPU isolation first then connect IO as
>> appropriate.
>>
>> Ross.
>>
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