You don't need memory barriers to implement an SPSC queue for x86. You can do a relaxed store to the queue followed by a release write to producer_idx. As long as consumer begins with an acquire load from producer_idx it is guaranteed to see all stores to the queue memory before producer_idx, according to the happens before ordering. There are no memory barriers on x86 for acquire/release semantics.
The release/acquire semantics have no meaning when used with different memory locations, but if used on producer_idx when synchronizing the consumer, and consumer_idx when synchronizing the producer, it should work. On Thu, Feb 15, 2018 at 8:29 AM, Avi Kivity <[email protected]> wrote: > Ever see mfence (aka full memory barrier, or std::memory_order_seq_cst) > taking the top row in a profile? Here's the complicated story of how we > took it down: > > > https://www.scylladb.com/2018/02/15/memory-barriers-seastar-linux/ > > -- > You received this message because you are subscribed to the Google Groups > "mechanical-sympathy" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "mechanical-sympathy" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
