From: Hitesh K. Patel <[email protected]> Using TE to periodically update command mode MIPI display instead of timer for B0. The DC will update it during display vblank. Added a kernel config to control CABC.
Signed-off-by: Jim Liu <[email protected]> Signed-off-by: Hitesh K. Patel <[email protected]> --- drivers/staging/mrst/drv/mdfld_dsi_dbi.c | 112 +++++++++++++++++++++----- drivers/staging/mrst/drv/mdfld_dsi_output.c | 30 +++++++- drivers/staging/mrst/drv/mdfld_output.c | 2 +- drivers/staging/mrst/drv/psb_drv.c | 16 ++++ drivers/staging/mrst/drv/psb_drv.h | 8 ++ drivers/staging/mrst/drv/psb_intel_drv.h | 1 + drivers/staging/mrst/drv/psb_intel_reg.h | 2 + drivers/staging/mrst/drv/psb_irq.c | 64 ++++++++++++++-- drivers/staging/mrst/drv/psb_powermgmt.c | 30 ++++++- drivers/staging/mrst/drv/pyr_cmd.c | 35 ++++++++- drivers/staging/mrst/drv/tpo_cmd.c | 45 +++++++++-- 11 files changed, 301 insertions(+), 44 deletions(-) diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dbi.c b/drivers/staging/mrst/drv/mdfld_dsi_dbi.c index d4dab42..d1fc581 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dbi.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dbi.c @@ -127,10 +127,13 @@ update_err: int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output * dbi_output, int mode) { struct drm_device * dev = dbi_output->dev; + struct drm_psb_private * dev_priv = dev->dev_private; u32 cb_phy = dbi_output->dbi_cb_phy; u8 * cb = (u8*)dbi_output->dbi_cb_addr; u32 * index; int reg_offset = (dbi_output->channel_num == 1) ? MIPIC_REG_OFFSET : 0; + u32 cmd_length = 0; + u32 cmd_len_reg_val = 0; int ret = 0; unsigned long flags; @@ -155,23 +158,60 @@ update_power_again: DRM_ERROR("Display module is busy\n"); goto set_power_err; } - + if(mode == DRM_MODE_DPMS_ON) { /*exit sleep mode*/ + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; *(cb + ((*index)++)) = exit_sleep_mode; - + + /*set display on*/ *index = 8; - + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; *(cb + ((*index)++)) = set_display_on; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + /* set tear effect on */ + *index = 16; + cmd_length = 2; + cmd_len_reg_val |= cmd_length << *index; + *(cb + ((*index)++)) = set_tear_on; + *(cb + ((*index)++)) = 0; + } } else { - /*set display off*/ - *(cb + ((*index)++)) = set_display_off; - - *index = 8; - - /*enter sleep mode*/ - *(cb + ((*index)++)) = enter_sleep_mode; + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + /*set tear effect off */ + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; + *(cb + ((*index)++)) = set_tear_off; + + /*set display off*/ + *index = 8; + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; + *(cb + ((*index)++)) = set_display_off; + + /*enter sleep mode*/ + *index = 16; + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; + *(cb + ((*index)++)) = enter_sleep_mode; + + cmd_length = 0x010101; + } else { + /*set display off*/ + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; + *(cb + ((*index)++)) = set_display_off; + + /*enter sleep mode*/ + cmd_length = 1; + cmd_len_reg_val |= cmd_length << *index; + *index = 8; + *(cb + ((*index)++)) = enter_sleep_mode; + } } spin_unlock_irqrestore(&dbi_output->cb_lock, flags); @@ -180,7 +220,7 @@ update_power_again: msleep(120); /*kick off*/ - REG_WRITE((MIPIA_CMD_LEN_REG + reg_offset), 0x0101); + REG_WRITE((MIPIA_CMD_LEN_REG + reg_offset), cmd_len_reg_val); REG_WRITE((MIPIA_CMD_ADD_REG + reg_offset), (cb_phy << CMD_MEM_ADDR_OFFSET) | BIT0 | BIT1); /*wait for 5ms*/ @@ -190,6 +230,10 @@ update_power_again: /*reset write pointer*/ *index = 0; + + /* reset command length */ + cmd_length = 0; + cmd_len_reg_val = 0; set_power_err: spin_unlock_irqrestore(&dbi_output->cb_lock, flags); @@ -299,6 +343,7 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output * dbi_output, int pipe { u32 reg_val; struct drm_device * dev = dbi_output->dev; + struct drm_psb_private * dev_priv = dev->dev_private; struct drm_crtc * crtc = dbi_output->base.base.crtc; struct psb_intel_crtc * psb_crtc = (crtc) ? to_psb_intel_crtc(crtc) : NULL; u32 dpll_reg = MRST_DPLL_A; @@ -327,6 +372,10 @@ void mdfld_dsi_dbi_enter_dsr (struct mdfld_dsi_dbi_output * dbi_output, int pipe if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) return; + /*disable te interrupts. */ + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mdfld_disable_te(dev, pipe); + /*disable plane*/ reg_val = REG_READ(dspcntr_reg); if(!(reg_val & DISPLAY_PLANE_ENABLE)) { @@ -464,19 +513,23 @@ void mdfld_dsi_dbi_exit_dsr (struct drm_device *dev, u32 update_src) dev_priv->dsr_fb_update |= update_src; - /*start timer*/ - mdfld_dbi_dsr_timer_start(dsr_info); + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + + if (dev_priv->dbi_panel_on) + mdfld_enable_te(dev, 0); + else if (dev_priv->dbi_panel_on2) + mdfld_enable_te(dev, 2); + } else + /*start timer*/ + mdfld_dbi_dsr_timer_start(dsr_info); } -/*timers for DSR*/ -static void mdfld_dsi_dbi_dsr_timer_func(unsigned long data) +/* Perodically update dbi panel */ +void mdfld_dbi_update_panel (struct drm_device *dev, int pipe) { - struct drm_device * dev = (struct drm_device *)data; struct drm_psb_private * dev_priv = dev->dev_private; struct mdfld_dbi_dsr_info * dsr_info = dev_priv->dbi_dsr_info; - struct timer_list * dsr_timer = &dsr_info->dsr_timer; struct mdfld_dsi_dbi_output ** dbi_output; - unsigned long flags; int i; dbi_output = dsr_info->dbi_outputs; @@ -510,9 +563,23 @@ static void mdfld_dsi_dbi_dsr_timer_func(unsigned long data) mdfld_dsi_dbi_enter_dsr(dbi_output[i], dbi_output[i]->channel_num ? 2 : 0); } } - return; } - +} + +/*timers for DSR*/ +static void mdfld_dsi_dbi_dsr_timer_func(unsigned long data) +{ + struct drm_device * dev = (struct drm_device *)data; + struct drm_psb_private * dev_priv = dev->dev_private; + struct mdfld_dbi_dsr_info * dsr_info = dev_priv->dbi_dsr_info; + struct timer_list * dsr_timer = &dsr_info->dsr_timer; + unsigned long flags; + + mdfld_dbi_update_panel (dev, 0); + + if (dsr_info->dsr_idle_count > 1) + return; + spin_lock_irqsave(&dsr_info->dsr_timer_lock, flags); if(!timer_pending(dsr_timer)){ dsr_timer->expires = jiffies + MDFLD_DSR_DELAY; @@ -574,8 +641,9 @@ int mdfld_dbi_dsr_init(struct drm_device * dev) dev_priv->dbi_dsr_info = dsr_info; } - /*init dsr refresh timer*/ - mdfld_dsi_dbi_dsr_timer_init(dev); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + /*init dsr refresh timer*/ + mdfld_dsi_dbi_dsr_timer_init(dev); PSB_DEBUG_ENTRY("successfully\n"); diff --git a/drivers/staging/mrst/drv/mdfld_dsi_output.c b/drivers/staging/mrst/drv/mdfld_dsi_output.c index 5ec1102..31ab4f6 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_output.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_output.c @@ -31,7 +31,30 @@ #include "mdfld_output.h" #define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100 -/*use command mode by default*/ + +/* get the CABC LABC from command line. */ +static int CABC_control = 1; + +#ifdef MODULE +module_param (CABC_control, int, 0644); +#else +static int __init parse_CABC_control(char *arg) +{ + /* CABC control can be passed in as a cmdline parameter */ + /* to enable this feature add cabc=1 to cmdline */ + /* to disable this feature add cabc=0 to cmdline */ + if (!arg) + return -EINVAL; + + if (!strcasecmp(arg, "0")) + CABC_control = 0; + else if (!strcasecmp (arg, "1")) + CABC_control = 1; + + return 0; +} +early_param ("CABC", parse_CABC_control); +#endif /** * make these MCS command global @@ -239,6 +262,8 @@ void mdfld_dsi_brightness_init (struct mdfld_dsi_config * dsi_config, int pipe) return; } + PSB_DEBUG_ENTRY("pipe = %d. \n", pipe); + dev = dsi_config->dev; dcsChannelNumber = dsi_config->channel_num; @@ -286,6 +311,9 @@ void mdfld_dsi_brightness_init (struct mdfld_dsi_config * dsi_config, int pipe) gen_ctrl_val |= MCS_SHORT_WRITE_1; REG_WRITE(hs_gen_ctrl_reg, gen_ctrl_val); + if (CABC_control == 0) + return; + /* Enable CABC */ mdfld_dsi_gen_fifo_ready (dev, gen_fifo_stat_reg, HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY); gen_ctrl_val = UI_IMAGE; diff --git a/drivers/staging/mrst/drv/mdfld_output.c b/drivers/staging/mrst/drv/mdfld_output.c index 8a1962c..76544cf 100644 --- a/drivers/staging/mrst/drv/mdfld_output.c +++ b/drivers/staging/mrst/drv/mdfld_output.c @@ -86,7 +86,7 @@ enum panel_type get_panel_type(struct drm_device *dev, int pipe) return TPO_CMD; } } else { - printk (KERN_ALERT "[GFX] Panel Parameter Passed in through Commandline\n"); + printk (KERN_ALERT "[GFX] Panel Parameter = %d, Passed in through Commandline\n", PanelID); return PanelID; } } diff --git a/drivers/staging/mrst/drv/psb_drv.c b/drivers/staging/mrst/drv/psb_drv.c index 069f98b..fceb26f 100644 --- a/drivers/staging/mrst/drv/psb_drv.c +++ b/drivers/staging/mrst/drv/psb_drv.c @@ -771,6 +771,20 @@ void mrst_get_fuse_settings(struct drm_device *dev) return; } +bool mid_get_pci_revID (struct drm_psb_private *dev_priv) +{ + uint32_t platform_rev_id = 0; + struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0)); + + /*get the revison ID, B0:D2:F0;0x08 */ + pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id); + dev_priv->platform_rev_id = (uint8_t) platform_rev_id; + pci_dev_put(pci_gfx_root); + PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id); + + return true; +} + bool mrst_get_vbt_data(struct drm_psb_private *dev_priv) { struct mrst_vbt *pVBT = &dev_priv->vbt_data; @@ -786,6 +800,7 @@ bool mrst_get_vbt_data(struct drm_psb_private *dev_priv) /*get the address of the platform config vbt, B0:D2:F0;0xFC */ pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address); + pci_dev_put(pci_gfx_root); DRM_INFO("drm platform config address is %x\n", platform_config_address); @@ -1244,6 +1259,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset) if (IS_MID(dev)){ mrst_get_fuse_settings(dev); mrst_get_vbt_data(dev_priv); + mid_get_pci_revID(dev_priv); } else { psb_get_core_freq(dev); psb_intel_opregion_init(dev); diff --git a/drivers/staging/mrst/drv/psb_drv.h b/drivers/staging/mrst/drv/psb_drv.h index 78cb913..72aec16 100644 --- a/drivers/staging/mrst/drv/psb_drv.h +++ b/drivers/staging/mrst/drv/psb_drv.h @@ -234,6 +234,9 @@ enum { #define PSB_WATCHDOG_DELAY (DRM_HZ * 2) #define PSB_LID_DELAY (DRM_HZ / 10) +#define MDFLD_PNW_A0 0x00 +#define MDFLD_PNW_B0 0x04 +#define MDFLD_PNW_C0 0x08 #if 1 /* MDFLD_JLIU7_DSR */ #if MDFLD_JLIU7_DPU_2 #define MDFLD_DSR_2D_3D BIT0 @@ -469,6 +472,9 @@ struct drm_psb_private { /* info that is stored from the gct */ struct gct_ioctl_arg gct_data; + /* pci revision id for B0:D2:F0 */ + uint8_t platform_rev_id; + /* *LVDS info */ @@ -1136,6 +1142,8 @@ void psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc); +extern int mdfld_enable_te(struct drm_device *dev, int pipe); +extern void mdfld_disable_te(struct drm_device *dev, int pipe); #ifdef MDFLD_HDCP extern int mdfld_irq_enable_hdmi_audio(struct drm_device *dev); extern int mdfld_irq_disable_hdmi_audio(struct drm_device *dev); diff --git a/drivers/staging/mrst/drv/psb_intel_drv.h b/drivers/staging/mrst/drv/psb_intel_drv.h index 9abe3fc..3a3bf2a 100644 --- a/drivers/staging/mrst/drv/psb_intel_drv.h +++ b/drivers/staging/mrst/drv/psb_intel_drv.h @@ -314,6 +314,7 @@ extern void mdfld_dbi_update_fb (struct drm_device *dev, int pipe); extern void mdfld_dbi_enter_dsr (struct drm_device *dev); extern void mdfld_dbi_exit_dsr (struct drm_device *dev, u32 update_src); #endif /* MDFLD_JLIU7_DSR */ +extern void mdfld_dbi_update_panel (struct drm_device *dev, int pipe); extern void mdfld_dsi_brightness_control (struct drm_device *dev, int pipe, int level); extern void mdfld_dsi_gen_fifo_ready (struct drm_device *dev, u32 gen_fifo_stat_reg, u32 fifo_stat); extern void mdfld_dsi_dbi_CB_ready (struct drm_device *dev, u32 mipi_command_address_reg, u32 gen_fifo_stat_reg); diff --git a/drivers/staging/mrst/drv/psb_intel_reg.h b/drivers/staging/mrst/drv/psb_intel_reg.h index 831c9bb..c192b1b 100644 --- a/drivers/staging/mrst/drv/psb_intel_reg.h +++ b/drivers/staging/mrst/drv/psb_intel_reg.h @@ -405,6 +405,7 @@ #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) #define PIPE_VBLANK_CLEAR (1 << 1) #define PIPE_VBLANK_STATUS (1 << 1) +#define PIPE_TE_STATUS (1UL<<6) #define PIPE_DPST_EVENT_STATUS (1UL<<7) #define PIPE_VSYNC_CLEAR (1UL<<9) #define PIPE_VSYNC_STATUS (1UL<<9) @@ -412,6 +413,7 @@ #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL<<11) #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) +#define PIPE_TE_ENABLE (1UL<<22) #define PIPE_DPST_EVENT_ENABLE (1UL<<23) #define PIPE_VSYNC_ENABL (1UL<<25) #define PIPE_HDMI_AUDIO_UNDERRUN (1UL<<26) diff --git a/drivers/staging/mrst/drv/psb_irq.c b/drivers/staging/mrst/drv/psb_irq.c index 93a02be..f85f671 100644 --- a/drivers/staging/mrst/drv/psb_irq.c +++ b/drivers/staging/mrst/drv/psb_irq.c @@ -237,6 +237,10 @@ static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe) mid_vblank_handler(dev, pipe); } + if (pipe_stat_val & PIPE_TE_STATUS) { + mdfld_dbi_update_panel (dev, pipe); + } + #ifdef MDFLD_HDCP if (pipe_stat_val & PIPE_HDMI_AUDIO_UNDERRUN_STATUS) { mdfld_pipe_hdmi_audio_underrun(dev); @@ -638,8 +642,8 @@ static int psb_vblank_do_wait(struct drm_device *dev, } #endif -/* Called from drm generic code, passed 'crtc' which - * we use as a pipe index +/* + * It is used to enable VBLANK interrupt */ int psb_enable_vblank(struct drm_device *dev, int pipe) { @@ -670,8 +674,8 @@ int psb_enable_vblank(struct drm_device *dev, int pipe) return 0; } -/* Called from drm generic code, passed 'crtc' which - * we use as a pipe index +/* + * It is used to disable VBLANK interrupt */ void psb_disable_vblank(struct drm_device *dev, int pipe) { @@ -701,9 +705,6 @@ u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) uint32_t reg_val = 0; uint32_t high1 = 0, high2 = 0, low = 0, count = 0; - high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; - low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; - switch (pipe) { case 0: break; @@ -755,6 +756,55 @@ psb_get_vblank_counter_exit: return count; } +/* + * It is used to enable TE interrupt + */ +int mdfld_enable_te(struct drm_device *dev, int pipe) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + unsigned long irqflags; + uint32_t reg_val = 0; + uint32_t pipeconf_reg = mid_pipeconf(pipe); + + PSB_DEBUG_ENTRY("pipe = %d, \n", pipe); + + if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_ONLY_IF_ON)) { + reg_val = REG_READ(pipeconf_reg); + ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); + } + + if (!(reg_val & PIPEACONF_ENABLE)) + return -EINVAL; + + spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); + + mid_enable_pipe_event(dev_priv, pipe); + psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); + + spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); + + return 0; +} + +/* + * It is used to disable TE interrupt + */ +void mdfld_disable_te(struct drm_device *dev, int pipe) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + unsigned long irqflags; + + PSB_DEBUG_ENTRY("\n"); + + spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); + + mid_disable_pipe_event(dev_priv, pipe); + psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE); + + spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); +} #ifdef MDFLD_HDCP int mdfld_irq_enable_hdmi_audio(struct drm_device *dev) diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c index 8d9a26d..7db1fdb 100644 --- a/drivers/staging/mrst/drv/psb_powermgmt.c +++ b/drivers/staging/mrst/drv/psb_powermgmt.c @@ -967,6 +967,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) u32 dpll = 0; u32 timeout = 0; u32 reg_offset = 0; + u8 param = 0; /* regester */ u32 dpll_reg = MRST_DPLL_A; @@ -1200,6 +1201,16 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) return -EINVAL; } + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + /*send set_tear_on DCS*/ + ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM); + + if(ret) { + DRM_ERROR("%s, set_tear_on faild. \n", __FUNCTION__); + return -EINVAL; + } + } + /*backlight operation*/ mdfld_dsi_brightness_init(dsi_config, pipe); @@ -1226,12 +1237,21 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) return -EINVAL; } -#ifdef CONFIG_MDFLD_DSI_DPU - /*start dpu timer*/ - mdfld_dbi_dpu_timer_start(dev_priv->dbi_dpu_info); + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + + if (dev_priv->dbi_panel_on && pipe == 0) + mdfld_enable_te(dev, 0); + + if (!dev_priv->dbi_panel_on && dev_priv->dbi_panel_on2 && (pipe == 2)) + mdfld_enable_te(dev, 2); + } else { +#ifdef CONFIG_MDFLD_DSI_DPU + /*start dpu timer*/ + mdfld_dbi_dpu_timer_start(dev_priv->dbi_dpu_info); #else - mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info); + mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info); #endif + } #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE mdfld_dsi_brightness_control(dev, pipe, psb_get_brightness(&bd)); @@ -1504,6 +1524,7 @@ static void ospm_suspend_pci(struct pci_dev *pdev) dev_priv->saveBSM = bsm; pci_read_config_dword(pci_gfx_root, 0xFC, &vbt); dev_priv->saveVBT = vbt; + pci_dev_put(pci_gfx_root); pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr); pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data); @@ -1535,6 +1556,7 @@ static bool ospm_resume_pci(struct pci_dev *pdev) pci_restore_state(pdev); pci_write_config_dword(pci_gfx_root, 0x5c, dev_priv->saveBSM); pci_write_config_dword(pci_gfx_root, 0xFC, dev_priv->saveVBT); + pci_dev_put(pci_gfx_root); /* retoring MSI address and data in PCIx space */ pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr); pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data); diff --git a/drivers/staging/mrst/drv/pyr_cmd.c b/drivers/staging/mrst/drv/pyr_cmd.c index 503e8ef..06618a1 100644 --- a/drivers/staging/mrst/drv/pyr_cmd.c +++ b/drivers/staging/mrst/drv/pyr_cmd.c @@ -143,6 +143,9 @@ static void pyr_dsi_dbi_set_power(struct drm_encoder * encoder, bool on) dev_priv->dbi_panel_on2 = true; } else { dev_priv->dbi_panel_on = true; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mdfld_enable_te(dev, 0); } } else { @@ -154,8 +157,18 @@ static void pyr_dsi_dbi_set_power(struct drm_encoder * encoder, bool on) if(pipe == 2) { dev_priv->dbi_panel_on2 = false; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mdfld_disable_te(dev, 2); } else { dev_priv->dbi_panel_on = false; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + mdfld_disable_te(dev, 0); + + if (dev_priv->dbi_panel_on2) + mdfld_enable_te(dev, 2); + } } ret = mdfld_dsi_dbi_update_power(dbi_output, DRM_MODE_DPMS_OFF); @@ -234,6 +247,7 @@ static void pyr_dsi_dbi_mode_set(struct drm_encoder * encoder, struct mdfld_dsi_config * dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder); struct mdfld_dsi_connector * dsi_connector = dsi_config->connector; int pipe = dsi_connector->pipe; + u8 param = 0; /*regs*/ u32 mipi_reg = MIPI; @@ -248,6 +262,11 @@ static void pyr_dsi_dbi_mode_set(struct drm_encoder * encoder, u32 v_active_area = mode->vdisplay; u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX); + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN); + + PSB_DEBUG_ENTRY("mipi_val =0x%x\n", mipi_val); + PSB_DEBUG_ENTRY("type %s\n", (pipe == 2) ? "MIPI2" : "MIPI"); PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay); @@ -292,6 +311,16 @@ static void pyr_dsi_dbi_mode_set(struct drm_encoder * encoder, DRM_ERROR("sent exit_sleep_mode faild\n"); goto out_err; } + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + /*send set_tear_on DCS*/ + ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM); + + if(ret) { + DRM_ERROR("%s - sent set_tear_on faild\n", __FUNCTION__); + goto out_err; + } + } /*do some init stuff*/ mdfld_dsi_brightness_init(dsi_config, pipe); @@ -375,9 +404,11 @@ static void pyr_dsi_dbi_commit(struct drm_encoder * encoder) #ifdef CONFIG_MDFLD_DSI_DPU mdfld_dbi_dpu_report_damage(dev, MDFLD_PLANEA, &rect); /*start dpu timer*/ - mdfld_dbi_dpu_timer_start(dev_priv->dbi_dpu_info); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mdfld_dbi_dpu_timer_start(dev_priv->dbi_dpu_info); #else - mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info); #endif } } diff --git a/drivers/staging/mrst/drv/tpo_cmd.c b/drivers/staging/mrst/drv/tpo_cmd.c index 6ac10a3..b159ac7 100644 --- a/drivers/staging/mrst/drv/tpo_cmd.c +++ b/drivers/staging/mrst/drv/tpo_cmd.c @@ -168,6 +168,9 @@ static void mdfld_dsi_dbi_set_power(struct drm_encoder * encoder, bool on) dev_priv->dbi_panel_on2 = true; } else { dev_priv->dbi_panel_on = true; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mdfld_enable_te(dev, 0); } } else { @@ -179,8 +182,18 @@ static void mdfld_dsi_dbi_set_power(struct drm_encoder * encoder, bool on) if(pipe == 2) { dev_priv->dbi_panel_on2 = false; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mdfld_disable_te(dev, 2); } else { dev_priv->dbi_panel_on = false; + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + mdfld_disable_te(dev, 0); + + if (dev_priv->dbi_panel_on2) + mdfld_enable_te(dev, 2); + } } ret = mdfld_dsi_dbi_update_power(dbi_output, DRM_MODE_DPMS_OFF); @@ -212,6 +225,7 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder * encoder, struct mdfld_dsi_config * dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder); struct mdfld_dsi_connector * dsi_connector = dsi_config->connector; int pipe = dsi_connector->pipe; + u8 param = 0; /*regs*/ u32 mipi_reg = MIPI; @@ -226,6 +240,11 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder * encoder, u32 v_active_area = mode->vdisplay; u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX); + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) + mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN); + + PSB_DEBUG_ENTRY("mipi_val =0x%x\n", mipi_val); + PSB_DEBUG_ENTRY("type %s\n", (pipe == 2) ? "MIPI2" : "MIPI"); PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay); @@ -258,18 +277,28 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder * encoder, msleep(20); - REG_WRITE(dspcntr_reg, dspcntr_val); - REG_READ(dspcntr_reg); + REG_WRITE(dspcntr_reg, dspcntr_val); + REG_READ(dspcntr_reg); - /*20ms delay before sending exit_sleep_mode*/ - msleep(20); + /*20ms delay before sending exit_sleep_mode*/ + msleep(20); - /*send exit_sleep_mode DCS*/ + /*send exit_sleep_mode DCS*/ ret = mdfld_dsi_dbi_send_dcs(dsi_output, exit_sleep_mode, NULL, 0, CMD_DATA_SRC_SYSTEM_MEM); if(ret) { DRM_ERROR("sent exit_sleep_mode faild\n"); goto out_err; } + + if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { + /*send set_tear_on DCS*/ + ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM); + + if(ret) { + DRM_ERROR("%s - sent set_tear_on faild\n", __FUNCTION__); + goto out_err; + } + } /*do some init stuff*/ mdfld_dsi_brightness_init(dsi_config, pipe); @@ -353,9 +382,11 @@ static void mdfld_dsi_dbi_commit(struct drm_encoder * encoder) #ifdef CONFIG_MDFLD_DSI_DPU mdfld_dbi_dpu_report_damage(dev, MDFLD_PLANEA, &rect); /*start dpu timer*/ - mdfld_dbi_dpu_timer_start(dev_priv->dbi_dpu_info); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mdfld_dbi_dpu_timer_start(dev_priv->dbi_dpu_info); #else - mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mdfld_dbi_dsr_timer_start(dev_priv->dbi_dsr_info); #endif } } -- 1.7.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
