The old policy will not enable MIC2BIAS on Moorstown platform by default, it's only enabled by selecting HS_MIC. Therefore when user selects DMIC and then inserts the jack, no interrupt will be seen.
The new policy will enable this bit by default, then no matter what the output device is, an interrupt will be generated. This behaviour is more likely what a user expects. Signed-off-by: Lu Guanqun <[email protected]> --- drivers/staging/intel_sst/intelmid_v2_control.c | 28 ++++++++++------------ 1 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/staging/intel_sst/intelmid_v2_control.c b/drivers/staging/intel_sst/intelmid_v2_control.c index bc2163a..b7be5a2 100644 --- a/drivers/staging/intel_sst/intelmid_v2_control.c +++ b/drivers/staging/intel_sst/intelmid_v2_control.c @@ -111,18 +111,19 @@ static int nc_init_card(void) {VOICEVOL, 0x0e, 0}, {HPLVOL, 0x06, 0}, {HPRVOL, 0x06, 0}, - {MICCTRL, 0x41, 0x00}, + {MICCTRL, 0x51, 0x00}, {ADCSAMPLERATE, 0x8B, 0x00}, {MICSELVOL, 0x5B, 0x00}, {LILSEL, 0x06, 0}, {LIRSEL, 0x46, 0}, {LOANTIPOP, 0x00, 0}, {DMICCTRL1, 0x40, 0}, + {AUXDBNC, 0xff, 0}, }; snd_pmic_ops_nc.card_status = SND_CARD_INIT_DONE; snd_pmic_ops_nc.master_mute = UNMUTE; snd_pmic_ops_nc.mute_status = UNMUTE; - sst_sc_reg_access(sc_access, PMIC_WRITE, 26); + sst_sc_reg_access(sc_access, PMIC_WRITE, 27); pr_debug("sst: init complete!!\n"); return 0; } @@ -852,7 +853,7 @@ static int nc_set_selected_input_dev(u8 value) pr_debug("sst: Selecting AMIC\n"); sc_access[0].reg_addr = 0x107; sc_access[0].value = 0x40; - sc_access[0].mask = MASK6|MASK4|MASK3|MASK1|MASK0; + sc_access[0].mask = MASK6|MASK3|MASK1|MASK0; sc_access[1].reg_addr = 0x10a; sc_access[1].value = 0x40; sc_access[1].mask = MASK6; @@ -867,9 +868,9 @@ static int nc_set_selected_input_dev(u8 value) case HS_MIC: pr_debug("sst: Selecting HS_MIC\n"); - sc_access[0].reg_addr = 0x107; - sc_access[0].mask = MASK6|MASK4|MASK3|MASK1|MASK0; - sc_access[0].value = 0x10; + sc_access[0].reg_addr = MICCTRL; + sc_access[0].mask = MASK6|MASK3|MASK1|MASK0; + sc_access[0].value = 0x00; sc_access[1].reg_addr = 0x109; sc_access[1].mask = MASK6; sc_access[1].value = 0x40; @@ -879,19 +880,16 @@ static int nc_set_selected_input_dev(u8 value) sc_access[3].reg_addr = 0x105; sc_access[3].value = 0x40; sc_access[3].mask = MASK6; - sc_access[4].reg_addr = AUXDBNC; - sc_access[4].mask = MASK7|MASK6|MASK5|MASK4|MASK3|MASK2|MASK1|MASK0; - sc_access[4].value = 0xff; - sc_access[5].reg_addr = ADCSAMPLERATE; - sc_access[5].mask = MASK7|MASK6|MASK5|MASK4|MASK3; - sc_access[5].value = 0xc8; - num_val = 6; + sc_access[4].reg_addr = ADCSAMPLERATE; + sc_access[4].mask = MASK7|MASK6|MASK5|MASK4|MASK3; + sc_access[4].value = 0xc8; + num_val = 5; break; case DMIC: pr_debug("sst: DMIC\n"); - sc_access[0].reg_addr = 0x107; - sc_access[0].mask = MASK6|MASK4|MASK3|MASK1|MASK0; + sc_access[0].reg_addr = MICCTRL; + sc_access[0].mask = MASK6|MASK3|MASK1|MASK0; sc_access[0].value = 0x0B; sc_access[1].reg_addr = 0x105; sc_access[1].value = 0x80; -- 1.7.2.3 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
