Langwell C0 adds a new SD host controller, i.e. SDHC2, to which a sdio wifi card is attached. Need to enable clock gating for that card so that SDHC2 can be runtime suspended and thus not block s0i3 any more.
Yong Wang (3): mmc: add per device quirk placeholder mmc: add MMC_QUIRK_BROKEN_CLK_GATING mmc: remove BROKEN_CLK_GATING quirk for AR6003 drivers/mmc/core/Makefile | 3 +- drivers/mmc/core/core.h | 2 + drivers/mmc/core/host.c | 5 +-- drivers/mmc/core/quirks.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ drivers/mmc/core/sdio.c | 1 + include/linux/mmc/card.h | 3 ++ 6 files changed, 93 insertions(+), 5 deletions(-) create mode 100644 drivers/mmc/core/quirks.c _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
