At 05:06 PM 08/03/99 -0800, Jason Stratos Papadopoulos wrote:
>On Sun, 7 Mar 1999 [EMAIL PROTECTED] wrote:
>> If one were to build a microprocessor SPECIFICALLY suited to LL testing,
>> what would the assembly instruction set look like? Approximately what
>> would the architecture look like? Speed shouldn't be an issue because
>> there's never enough anyway and we're trying to work smarter not harder.
>[...]
>Unfortunately, I just described the UltraSPARC, the Alpha and the PII.
>If you *insist* on a do-it-yourself job, look into Analog Devices'
>SHARC line of DSP chips, they kick butt for high-bandwidth integer math.
I disagree. There are a large number of features that could be
eliminated from modern CPUs if we only wanted to run LL tests, and there
are other features -- larger registers, larger multipliers -- which should
be added.
If I were designing a CPU specifically for LL tests, I'd include
a) a memory prefectch instruction and a 32K prefetch cache (ie, it only
caches data which it was told to prefetch).
b) 16 32-bit control/address registers and 16 128-bit data registers
c) 128x128 bit (pipelined) multiply modulo a convinient 128-bit prime
d) 128-bit add/subtract modulo said prime
e) a VLIW architecture.
Then I would run FFTs over GF(hardwired prime).
I would not include non-blocking caches, branch prediction, out of order
execution, register renaming, or any other similar features, since they are
designed to help out unpredictable, compiler-generated code; FFTs are
highly predictable, and the code for them can be optimized well.
Colin Percival
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