>The Athlon not only supports SMP, but it does it the, IMHO, Right Way(tm).
>They use a point to point bus between the processor and the core logic.
>Hence, a SMP Athlon system has no shared bus. Each processor gets
>a pipe to
>the core logic and it has however many pipes to memory/IO that it wants.
>This is what you have to do to scale SMP very high, anyway. I think the
>Intel chips force this for #CPUs>4, too. Maybe it's 2--I can't remember
>right now.
The new >4 CPU systems using the Profusion architecture should handle things
a lot better for x86 CPU's. I didn't get too much hands on, but at the
Compaq System Engineer conference last summer, I got to fiddle with a few
Proliant 8000's and 8500's just a few weeks before they were publicly
announced. Too bad I didn't have NTPrime with me, but then, if someone like
me gets caught with that, they probably consider it contraband. :)
But they did have some impressive stuff going on them...the SQL setups were
really nice, but I'm not sure how much those stress out the
cache...oh...they were using 450MHz PII Xeon's with 1MB of L2. That extra
MB of L2 cache, to get you to 2MB, adds a lot of cost though...
I just checked on Pricewatch...my goodness, how prices have dropped since
just 6 months ago. The 2MB version of the 450MHz PII Xeon is going for a
mere $750 or so...while the 1MB version can be had for $425. Hmmm...
The PIII Xeon's (500MHz) are about $1500 for the 2MB version, and around
$1000 for the 1MB. That's about what the PII Xeon's were going for 6 months
ago...
I do wonder what the speeds would be like for Prime95/NTPrime on a 1MB vs.
2MB Xeon... Anyone have the chance to test that out?
Aaron
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