On Sun, 9 Sep 2001, George Woltman wrote:
> c) At these large FFT sizes, we are now putting pressure on the
> TLB caches. The TLB maps a virtual address into a physical address.
> Intel chips keep track of 64 TLB entries, each entry maps to a 4KB
> page.
> IIRC, Athlon CPUs have an even smaller TLB cache. A TLB cache miss
> does add some time to a memory access.
The Athlon has a 32-entry TLB but also has a 256 entry "level 2" TLB. I
don't know how long a TLB reload from L2 cache takes.
jasonp
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