Module: Mesa Branch: master Commit: 4d2b392a0ac597f8b7f88006746660e8f0fe09ea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d2b392a0ac597f8b7f88006746660e8f0fe09ea
Author: Roland Scheidegger <[email protected]> Date: Fri Jun 19 22:55:34 2009 +0200 radeon: fix cube maps for non-mm path drm cmd checker would refuse cube emits also fix an issue in the cs path which would calculate the register offset off by one dword. Only same testing done as original code (none except compile tested). --- src/mesa/drivers/dri/radeon/radeon_state_init.c | 35 +++++++++++++++++++++- 1 files changed, 33 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index f5d4189..c517487 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -465,6 +465,34 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) { r100ContextPtr r100 = R100_CONTEXT(ctx); BATCH_LOCALS(&r100->radeon); + uint32_t dwords = 3; + int i = atom->idx, j; + radeonTexObj *t = r100->state.texture.unit[i].texobj; + radeon_mipmap_level *lvl; + + if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) + return; + + if (!t) + return; + + if (!t->mt) + return; + + BEGIN_BATCH_NO_AUTOSTATE(dwords + (5 * 3)); + OUT_BATCH_TABLE(atom->cmd, 3); + lvl = &t->mt->levels[0]; + for (j = 0; j < 5; j++) { + OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, + RADEON_GEM_DOMAIN_VRAM, 0, 0); + } + END_BATCH(); +} + +static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) +{ + r100ContextPtr r100 = R100_CONTEXT(ctx); + BATCH_LOCALS(&r100->radeon); uint32_t dwords = 2; int i = atom->idx, j; radeonTexObj *t = r100->state.texture.unit[i].texobj; @@ -490,7 +518,7 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) OUT_BATCH_TABLE(atom->cmd, 2); lvl = &t->mt->levels[0]; for (j = 0; j < 5; j++) { - OUT_BATCH(CP_PACKET0(base_reg + (4 * (j-1)), 0)); + OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, RADEON_GEM_DOMAIN_VRAM, 0, 0); } @@ -661,7 +689,10 @@ void radeonInitState( r100ContextPtr rmesa ) ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 ); ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 ); for (i = 0; i < 3; i++) - rmesa->hw.cube[i].emit = cube_emit; + if (rmesa->radeon.radeonScreen->kernel_mm) + rmesa->hw.cube[i].emit = cube_emit_cs; + else + rmesa->hw.cube[i].emit = cube_emit; } else { _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
